參數(shù)資料
型號: L3G4200DHTR
廠商: STMICROELECTRONICS
元件分類: 模擬信號調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PBGA16
封裝: 4 X 4 MM, 1.10 MM HEIGHT, ROHS COMPLIANT, PLASTIC, LGA-16
文件頁數(shù): 14/28頁
文件大?。?/td> 949K
代理商: L3G4200DHTR
L3G4200DH
Digital interfaces
Doc ID 17300 Rev 1
21/28
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit
(MSb) first. If a receiver cannot receive another complete byte of data until it has performed
some other function, it can hold the clock line SCL LOW to force the transmitter into a wait
state. Data transfer only continues when the receiver is ready for another byte and releases
the data line. If a slave receiver does not acknowledge the slave address (i.e., it is not able
to receive because it is performing some real-time function) the data line must be left HIGH
by the slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA
line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
In order to read multiple bytes, it is necessary to assert the most significant bit of the sub-
address field. In other words, SUB(7) must be equal to 1, while SUB(6-0) represents the
address of the first register to be read.
In the presented communication format, MAK is “master acknowledge” and NMAK is “no
master acknowledge”.
4.2
SPI bus interface
The SPI is a bus slave. The SPI allows writing and reading of the registers of the device. The
serial interface interacts with the external world through 4 wires: CS, SPC, SDI and SDO.
Table 14.
Transfer when master is writing multiple bytes to slave
Master
ST
SAD + W
SUB
DATA
SP
Slave
SAK
Table 15.
Transfer when master is receiving (reading) one byte of data from slave
Master
ST
SAD + W
SUB
SR
SAD + R
NMAK
SP
Slave
SAK
DATA
Table 16.
Transfer when master is receiving (reading) multiple bytes of data from slave
Master ST SAD+W
SUB
SR SAD+R
MAK
NMAK
SP
Slave
SAK
SAK DATA
DATA
相關(guān)PDF資料
PDF描述
L3G4200D SPECIALTY ANALOG CIRCUIT, PBGA16
L5981 1 A SWITCHING REGULATOR, 1000 kHz SWITCHING FREQ-MAX, PDSO8
L5981TR 1 A SWITCHING REGULATOR, 1000 kHz SWITCHING FREQ-MAX, PDSO8
L5985 2 A SWITCHING REGULATOR, 1000 kHz SWITCHING FREQ-MAX, PDSO8
L5985TR 2 A SWITCHING REGULATOR, 1000 kHz SWITCHING FREQ-MAX, PDSO8
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