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參數(shù)資料
| 型號： | L3G4200DHTR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PBGA16 |
| 封裝： | 4 X 4 MM, 1.10 MM HEIGHT, ROHS COMPLIANT, PLASTIC, LGA-16 |
| 文件頁數(shù)： | 11/28頁 |
| 文件大?。?/td> | 949K |
| 代理商： | L3G4200DHTR |
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L3G4200DH
Digital interfaces
Doc ID 17300 Rev 1
19/28
4
Digital interfaces
The registers embedded in the L3G4200DH may be accessed through both the I2C and SPI
serial interfaces. The latter may be software-configured to operate either in 3-wire or 4-wire
interface mode.
The serial interfaces are mapped onto the same pins. To select/exploit the I2C interface, the
CS line must be tied high (i.e., connected to Vdd_IO).
4.1
I2C serial interface
The L3G4200DH I2C is a bus slave. The I2C is employed to write data to registers whose
content can also be read back.
The relevant I2C terminology is given in the table below.
There are two signals associated with the I2C bus: the serial clock line (SCL) and the serial
data line (SDA). The latter is a bidirectional line used for sending and receiving the data
to/from the interface. Both lines must be connected to Vdd_IO through an external pull-up
resistor. When the bus is free both the lines are high.
The I2C interface is compliant with fast mode (400 kHz) I2C standards as well as with normal
mode.
Table 10.
Serial interface pin description
Pin name
Pin description
CS
SPI enable
I2C/SPI mode selection (1: I2C mode; 0: SPI enabled)
SCL/SPC
I2C serial clock (SCL)
SPI serial port clock (SPC)
SDA/SDI/SDO
I2C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
SDO
SPI serial data output (SDO)
I2C least significant bit of the device address
Table 11.
I2C terminology
Term
Description
Transmitter
The device which sends data to the bus
Receiver
The device which receives data from the bus
Master
The device which initiates a transfer, generates clock signals and terminates a
transfer
Slave
The device addressed by the master
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