參數(shù)資料
型號(hào)： KSZ9021GQ
廠商： Micrel Inc
文件頁(yè)數(shù)： 22/59頁(yè)
文件大小： 0K
描述： IC TXRX 10/100/1000 3.3V 128PQFP
標(biāo)準(zhǔn)包裝： 66
類型： 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 8/8
規(guī)程： 千兆位以太網(wǎng)
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-PQFP（14x20）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 1081 (CN2011-ZH PDF)
其它名稱： 576-3396
Micrel, Inc.
KSZ9021GQ
September 2010
29
M9999-091010-1.2
MII Management (MIIM) Interface
The KSZ9021GQ supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input /
Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the KSZ9021GQ. An
external device with MIIM capability is used to read the PHY status and/or configure the PHY settings. Further detail on
the MIIM interface can be found in Clause 22.2.4.5 of the IEEE 802.3 Specification.
The MIIM interface consists of the following:
A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
A specific protocol that operates across the aforementioned physical connection that allows an external controller
to communicate with one or more KSZ9021GQ device. Each KSZ9021GQ device is assigned a PHY address
between 1 and 31 by the PHYAD[4:0] strapping pins.
A 32 register address space to access the KSZ9021GQ IEEE Defined Registers, Vendor Specific Registers and
Extended Registers. See Register Map section.
The following table shows the MII Management frame format for the KSZ9021GQ.
Preamble
Start of
Frame
Read/Write
OP Code
PHY
Address
Bits [4:0]
REG
Address
Bits [4:0]
TA
Data
Bits [15:0]
Idle
Read
32 1’s
01
10
AAAAA
RRRRR
Z0
DDDDDDDD_DDDDDDDD
Z
Write
32 1’s
01
AAAAA
RRRRR
10
DDDDDDDD_DDDDDDDD
Z
Table 5. MII Management Frame Format – for KSZ9021GQ
Interrupt (INT_N)
INT_N (pin 101) is an optional interrupt signal that is used to inform the external controller that there has been a status
update in the KSZ9021GQ PHY register. Bits [15:8] of register 27 (1Bh) are the interrupt control bits to enable and disable
the conditions for asserting the INT_N signal. Bits [7:0] of register 27 (1Bh) are the interrupt status bits to indicate which
interrupt conditions have occurred. The interrupt status bits are cleared after reading register 27 (1Bh).
Bit 14 of register 31 (1Fh) sets the interrupt level to active high or active low. The default is active low.
The MII management bus option gives the MAC processor complete access to the KSZ9021GQ control and status
registers. Additionally, an interrupt pin eliminates the need for the processor to poll the PHY for status change.
LED Mode
The KSZ9021GQ provides six programmable LED output pins (LED1 thru LED6) that are configurable to support three
LED modes. Bits [7:6] of register 17 (11h) are the LED Mode Select [1:0] bits, and are defined as follow:
00 = Reserved – not used
10 = 4-LED Configuration
01 = 5-LED Configuration
11 = 6-LED Configuration (default setting after power-up / reset)
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KSZ9021RN 功能描述:以太網(wǎng) IC Gigabit Ethernet Transceiver with RGMII, Lead Free RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
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