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參數(shù)資料
| 型號(hào)： | KSZ8995XA |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 24/51頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC SWITCH 10/100 5PORT 128PQFP |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 系列： | * |
| 類(lèi)型： | * |
| 應(yīng)用： | * |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-PQFP（14x20） |
| 包裝： | 托盤(pán) |
| 產(chǎn)品目錄頁(yè)面： | 1081 (CN2011-ZH PDF) |
| 配用： | 576-1642-ND - BOARD EVALUATION FOR KSZ8995XA |
| 其它名稱(chēng)： | 576-1042 |
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KS8995XA
Micrel, Inc.
M9999-051305
30
May 2005
Address
Name
Description
Mode
Default
Register 2 (0x02): Global Control 0 (continued)
2
Buffer share mode
1 = buffer pool is shared by all ports. A port can use
R/W
0x1
more buffer when other ports are not busy.
0 = a port is only allowed to use 1/5 of the buffer pool.
1
UNH mode
1 = the switch will drop packets with 0x8808 in T/L
R/W
0
filed, or DA=01-80-C2-00-00-01.
0 = the switch will drop packets qualified as
“flow control” packets.
0
Link change age
1 = link change from “l(fā)ink” to “no link” will cause fast
R/W
0
aging (<800s) to age address table faster. After an
age cycle is complete, the age logic will return to
normal (300 ±75 seconds). Note: If any port is
unplugged, all addresses will be automatically aged
out.
Register 3 (0x03): Global Control 1
7
Pass all frames
1 = switch all packets including bad ones. Used solely
R/W
0
for debugging purpose. Works in conjunction with
sniffer mode.
6
Reserved
R/W
0
5
IEEE 802.3x transmit
0 = will enable transmit flow control based on AN result
R/W
Pin PMRXD3 strap
flow control disable
1 = will not enable transmit flow control regardless of
option. Pull-down (0):
AN result.
Enable TX flow
control. Pull-up (1):
Disable TX/RX flow
control.
Note: PMRXD3
has internal pull-
down.
4
IEEE 802.3x receive
0 = will enable receive flow control based on AN result
R/W
Pin PMRXD3 strap
flow control disable
1 = will not enable receive flow control regardless of
option. Pull-down (0):
AN result.
Enable RX flow
control. Pull-up (1):
Note: Bit 5 and bit 4 default values are controlled by
Disable TX/RX flow
the same pin, but they can be programmed
control.
independently.
Note: PMRXD3
has internal pull-
down.
3
Frame length field
1 = will check frame length field in the IEEE packets.
R/W
0
check
If the actual length does not match, the packet will be
dropped. (for L/T < 1500)
2
Aging enable
1 = Enable age function in the chip
R/W
Pin LED[5][2] strap
0 = Disable aging function
option. Pull-down
(0): Aging disable.
Pull-up (1): Aging
Enable.
Note: LED[5][2]
has internal pull-up.
1
Fast age enable
1 = turn on fast age (800s)
R/W
0
Aggressive back
1 = enable more aggressive back off algorithm in half-
R/W
Pin PMRXD0 strap
off enable
duplex mode to enhance performance. This is not an
option. Pull-down (0):
IEEE standard.
Disable aggressive
back off. Pull-up
(1): Aggressive
backoff. Note:
PMRXD0
has internal pull-
down.
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