參數(shù)資料
型號(hào)： KSZ8995MI
廠商： Micrel Inc
文件頁數(shù)： 39/76頁
文件大?。?/td> 0K
描述： IC SWITCH 5-PORT 10/100 128PQFP
標(biāo)準(zhǔn)包裝： 66
系列： *
類型： *
應(yīng)用： *
安裝類型： 表面貼裝
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-PQFP（14x20）
包裝： 托盤
產(chǎn)品目錄頁面： 1081 (CN2011-ZH PDF)
其它名稱： 576-2127
KSZ8995MI-ND
KS8995M
Micrel, Inc.
M9999-062309
44
June 2009
Port Registers
The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are
the same for all ports, but the address for each port is different, as indicated.
Register 16 (0x10): Port 1 Control 0
Register 32 (0x20): Port 2 Control 0
Register 48 (0x30): Port 3 Control 0
Register 64 (0x40): Port 4 Control 0
Register 80 (0x50): Port 5 Control 0
Address
Name
Description
Mode
Default
7
Broadcast storm
1, enable broadcast storm protection for ingress packets
R/W
0
protection enable
on the port.
0, disable broadcast storm protection.
6
Diffserv priority
1, enable DiffServ priority classification for ingress
R/W
0
classification enable
packets on port.
0, disable DiffServ function.
5
802.1p priority
1, enable 802.1p priority classification for ingress
R/W
0
classification enable
packets on port.
0, disable 802.1p.
4
Port-based priority
1, ingress packets on the port will be classified as high
R/W
0
classification enable
priority if “DiffServ” or “802.1p” classification is not
enabled or fails to classify.
0, ingress packets on port will be classified as low priority
if “DiffServ” or “802.1p” classification is not enabled or
fails to classify.
Note: “DiffServ”, “802.1p” and port priority can be
enabled at the same time. The OR’ed result of 802.1p
and DSCP overwrites the port priority.
3
Reserved
R/W
0
2
Tag insertion
1, when packets are output on the port, the switch will
R/W
0
add 802.1q tags to packets without 802.1q tags when
received. The switch will not add tags to packets already
tagged. The tag inserted is the ingress port’s “port VID”
0, disable tag insertion.
1
Tag removal
1, when packets are output on the port, the switch will
R/W
0
remove 802.1q tags from packets with 802.1q tags
when received. The switch will not modify packets
received without tags.
0, disable tag removal.
0
Priority enable
1, the port output queue is split into high and low
R/W
0
priority queues.
0, single output queue on the port. There is no priority
differentiation even though packets are classified into
high or low priority.
Register 17 (0x11): Port 1 Control 1
Register 33 (0x21): Port 2 Control 1
Register 49 (0x31): Port 3 Control 1
Register 65 (0x41): Port 4 Control 1
Register 81 (0x51): Port 5 Control 1
Address
Name
Description
Mode
Default
7
Sniffer port
1, Port is designated as sniffer port and will transmit
R/W
0
packets that are monitored.
0, Port is a normal port.
6
Receive sniff
1, All the packets received on the port will be marked
R/W
0
as “monitored packets” and forwarded to the designated
“sniffer port.”
0, no receive monitoring.
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