- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄11593 > KSZ8893FQL-FX (Micrel Inc)IC SWITCH ETH 3PORT 128-PQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | KSZ8893FQL-FX |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 60/117頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC SWITCH ETH 3PORT 128-PQFP |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 控制器類型： | 以太網(wǎng)開(kāi)關(guān)控制器 |
| 接口： | MII，RMII，SNI |
| 電源電壓： | 3.1 V ~ 3.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-PQFP（14x20） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁(yè)面： | 1081 (CN2011-ZH PDF) |
| 配用： | 576-1603-ND - EVAL KIT EXPERIMENTAL KSZ8893MQL |
| 其它名稱： | 576-3273 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)當(dāng)前第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)
Micrel, Inc.
KSZ8893FQL
October 2007
47
M9999-101607-1.3
DiffServ-Based Priority
DiffServ-based priority uses the ToS registers (registers 96 to 111) in the Advanced Control Registers section. The ToS
priority control registers implement a fully decoded, 64-bit Differentiated Services Code Point (DSCP) register to
determine packet priority from the 6-bit ToS field in the IP header. When the most significant 6 bits of the ToS field are
fully decoded, the resultant of the 64 possibilities is compared with the corresponding bits in the DSCP register to
determine priority.
Rate Limiting Support
The KSZ8893FQL supports hardware rate limiting from 64 Kbps to 88 Mbps, independently on the “receive side” and
on the “transmit side” on a per port basis. For 10Base-T, a rate setting above 10 Mbps means the rate is not limited. On
the receive side, the data receive rate for each priority at each port can be limited by setting up Ingress Rate Control
Registers. On the transmit side, the data transmit rate for each priority queue at each port can be limited by setting up
Egress Rate Control Registers. The size of each frame has options to include minimum IFG (Inter Frame Gap) or
Preamble byte, in addition to the data field (from packet DA to FCS).
For ingress rate limiting, KSZ8893FQL provides options to selectively choose frames from all types, multicast,
broadcast, and flooded unicast frames. The KSZ8893FQL counts the data rate from those selected type of frames.
Packets are dropped at the ingress port when the data rate exceeds the specified rate limit.
For egress rate limiting, the Leaky Bucket algorithm is applied to each output priority queue for shaping output traffic.
Inter frame gap is stretched on a per frame base to generate smooth, non-burst egress traffic. The throughput of each
output priority queue is limited by the egress rate specified.
If any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in the
output queue and packet memory. After the memory of the queue or the port is used up, packet dropping or flow control
will be triggered. As a result of congestion, the actual egress rate may be dominated by flow control/dropping at the
ingress end, and may be therefore, slightly less than the specified egress rate.
To reduce congestion, it is a good practice to make sure the egress bandwidth exceeds the ingress bandwidth.
Unicast MAC Address Filtering
The unicast MAC address filtering function works in conjunction with the static MAC address table. First, the static MAC
address table is used to assign a dedicated MAC address to a specific port. If a unicast MAC address is not recorded in
the static table, it is also not learned in the dynamic MAC table. The KSZ8893FQL is then configured with the option to
either filter or forward unicast packets for an unknown MAC address. This option is enabled and configured in register
14.
This function is useful in preventing the broadcast of unicast packets that could degrade the quality of the port in
applications such as voice over Internet Protocol (VoIP).
Configuration Interface
The KSZ8893FQL can operate as both a managed switch and an unmanaged switch.
In unmanaged mode, the KSZ8893FQL is typically programmed using an EEPROM. If no EEPROM is present, the
KSZ8893FQL is configured using its default register settings. Some default settings are configured via strap-in pin
options. The strap-in pins are indicated in the “KSZ8893FQL Pin Description and I/O Assignment” table.
I2C Master Serial Bus Configuration
With an additional I
2C (“2-wire”) EEPROM, the KSZ8893FQL can perform more advanced switch features like
“broadcast storm protection” and “rate control” without the need of an external processor.
For KSZ8893FQL I
2C Master configuration, the EEPROM stores the configuration data for register 0 to register 120 (as
defined in the KSZ8893FQL register map) with the exception of the “Read Only” status registers. After the de-assertion
of reset, the KSZ8893FQL sequentially reads in the configuration data for all 121 registers, starting from register 0. The
configuration access time (tprgm) is less than 15 ms, as depicted in the following figure.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PIC12C509AT-04E/SN | IC MCU OTP 1KX12 8SOIC |
| PIC16F1829T-I/SS | MCU PIC 14K FLASH 1K RAM 20SSOP |
| V72A24C400BL3 | CONVERTER MOD DC/DC 24V 400W |
| PIC16F677-E/SS | IC PIC MCU FLASH 2KX14 20SSOP |
| V72A24C400BL2 | CONVERTER MOD DC/DC 24V 400W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KSZ8893FQLI-FX | 功能描述:以太網(wǎng) IC 3-Port Ethernet Switch w MII/RMII Interface + 100FX (I-Temp, Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8893MBL | 功能描述:以太網(wǎng) IC 2+1 Port 10/100 Switch w/Tranceivers & Frame Buffers, 128-Ld PQFP(Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8893MBL TR | 功能描述:以太網(wǎng) IC 2+1 Port 10/100 Switch w/Tranceivers & Frame Buffers, 100-Ball LFBGA (Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8893MBLI | 功能描述:以太網(wǎng) IC 2+1 Port 10/100 Switch w/ Tranceivers & Frame Buffers (Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8893MQL | 功能描述:以太網(wǎng) IC 2+1 Port 10/100 Switch w/Tranceivers & Frame Buffers, 128-Ld PQFP(Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。