參數(shù)資料
型號(hào): KSZ8851SNL TR
廠商: Micrel Inc
文件頁(yè)數(shù): 4/80頁(yè)
文件大?。?/td> 0K
描述: IC CTLR MAC/PHY NON-PCI 32-MLF
產(chǎn)品培訓(xùn)模塊: KSZ8851 10/100 Embedded Controllers
標(biāo)準(zhǔn)包裝: 1
控制器類型: 以太網(wǎng)控制器,MAC/PHY
接口: 總線
電源電壓: 1.8V,2.5V,3.3V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,32-MLF?
供應(yīng)商設(shè)備封裝: 32-MLF?(5x5)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面: 1081 (CN2011-ZH PDF)
配用: 576-3293-ND - BOARD EVALUATION KSZ8851SNL
其它名稱: 576-3299-6
Micrel, Inc.
KSZ8851SNL/SNLI
August 2009
12
M9999-083109-2.0
Pin Number
Pin Name
Type
Pin Function
Hardware reset pin (active Low). This reset input must be held low for a minimum of 10ms
after stable supply voltage 3.3V.
20
X1
I
21
X2
O
25MHz crystal or oscillator clock connection.
Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V tolerant
oscillator and X2 is a no connect.
Note: Clock requirement is +/- 50ppm for either crystal or oscillator.
22
DGND
Gnd
Digital IO ground
23
VDD_D1.8
P
1.8V digital power supply from VDD_CO1.8 (pin 5) with appropriate filtering. If VDD_IO is
1.8V, this pin must be supplied power from the same source as pins 25 and 30 (VDD_IO)
with appropriate filtering.
24
DGND
Gnd
Digital IO ground
25
VDD_IO
P
3.3V, 2.5V or 1.8V digital VDD input power supply for IO with well decoupling capacitors.
26
CSN
Ipu
SPI slave mode: Chip Select Not
Active low input pin for SPI interface.
27
SO
O
SPI slave mode: Serial data out for SPI interface. This SO is tri-stated output when CSN
is negated and this pin must have external 4.7K pull-up to keep the SO line high while the
driver is tri-stated.
28
SCLK
I
SPI slave mode: Serial clock input for SPI interface. This clock speed can run up to
40MHz.
29
DGND
Gnd
Digital IO ground
30
VDD_IO
P
3.3V, 2.5V or 1.8V digital VDD input power supply for IO with well decoupling capacitors.
31
SI
Ipd
SPI slave mode: Serial data in for SPI interface.
32
LED1
Opu
Programmable LED1 output to indicate PHY activity/status (see LED0 description at pin1)
Legend:
P = Power supply
Gnd = Ground
I/O = Bi-directional I = Input O = Output.
Ipd = Input with internal pull-down (58K +/-30%).
Ipu = Input with internal pull-up (58K +/-30%).
Opd = Output with internal pull-down (58K +/-30%).
Opu = Output with internal pull-up (58K +/-30%).
Ipu/O = Input with internal pull-up (58K +/-30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (58K +/-30%) during power-up/reset; output pin otherwise.
Strapping Options
Pin Number
Pin Name
Type
Pin Function
6
EED_IO
Ipd/O
EEPROM select:
Pull-up = EEPROM present
Floating (NC) or Pull-down = EEPROM not present (default)
During power-up / reset, this pin value is latched into register CCR, bit 9
Note: Ipd/O = Input with internal pull-down (58K +/-30%) during power-up/reset; output pin otherwise.
Pin strap-ins are latched during power-up or reset.
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