參數(shù)資料
型號(hào)： KSZ8841-16MBLI
廠商： Micrel Inc
文件頁數(shù)： 34/105頁
文件大?。?/td> 0K
描述： IC MAC CTRLR 8/16BIT 100-LBGA
標(biāo)準(zhǔn)包裝： 260
控制器類型： 以太網(wǎng)控制器，MAC
接口： 總線
電源電壓： 3.1 V ~ 3.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LBGA
供應(yīng)商設(shè)備封裝： 100-LFBGA
包裝： 散裝
Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
October 2007
34
M9999-102207-1.6
Signal
Type
(1)
Function
Common Signals
A[15:1]
I
Address
AEN
I
Address Enable
Address Enable asserted indicates memory address on the bus for DMA access
and since the device is an I/O device, address decoding is only enabled when AEN
is Low.
BE3N, BE2N,
BE1N, BE0N
I
Byte Enable
BE0N
BE1N
BE2N
BE3N
Description
0
32-bit access
0
1
Lower 16-bit (D[15:0]) access
1
0
Higher 16-bit (D[31:16]) access
0
1
Byte 0 (D[7:0]) access
1
0
1
Byte 1 (D[15:8]) access
1
0
1
Byte 2 (D[23:16]) access
1
0
Byte 3 (D[31:24]) access
Note 1: BE3N, BE2N, BE1N and BE0N are ignored when DATACSN is low because
32 bit transfers are assumed.
Note 2: BE2N and BE3N are valid only for the KSZ8841-32 mode, and are No
Connect for the KSZ8841-16 mode.
D[31:16]
I/O
Data
For KSZ8841M-32 mode only.
D[15:0]
I/O
Data
For both KSZ8841-32 and KSZ8841-16 Modes
ADSN
I
Address Strobe
The rising edge of ADSN is used to latch A[15:1], AEN, BE3N, BE2N, BE1N and
BE0N.
LDEVN
O
Local Device
This signal is a combinatorial decode of AEN and A[15:4]. This A[15:4] is used to
compare against the Base Address Register.
DATACSN
I
Data Register Chip Select (For KSZ8841-32MQL Mode only)
This signal is used for central decoding architecture (mostly for embedded
application). When asserted, the device’s local decoding logic is ignored and the 32-
bit access to QMU Data Register is assumed.
INTR
O
Interrupt
Synchronous Transfer Signals
VLBUSN
I
VLBUS
VLBUSN = 0, VLBus-like cycle.
VLBUSN = 1, burst cycle (both host/system and KSZ8841M can insert wait state)
CYCLEN
I
CYCLEN
For VLBus-like access: used to sample SWR when asserted.
For burst access: used to connect to IOWC# bus signal to indicate burst write.
SWR
I
Write/Read
For VLBus-like access: used to indicate write (High) or read (Low) transfer.
For burst access: used to connect to IORC# bus signal to indicate burst read.
SRDYN
O
Synchronous Ready
For VLBus-like access: exactly the same signal definition of nSRDY in VLBus.
For burst access: insert wait state by KSZ8841M whenever necessary during the
Data Register access.
RDYRTNN
I
Ready Return
For VLBus-like access: exactly like RDYRTNN signal in VLBus to end the cycle.
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