KS8721B/BT Micrel, Inc. Collision: Whenever the line state is half-duplex and the transmitter and rece" />
參數(shù)資料
型號(hào)： KSZ8721BI
廠商： Micrel Inc
文件頁(yè)數(shù)： 5/32頁(yè)
文件大?。?/td> 0K
描述： IC TXRX PHY 10/100 2.5V 48SSOP
標(biāo)準(zhǔn)包裝： 30
類型： 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 1/1
規(guī)程： MII，RMII
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
封裝/外殼： 48-BSSOP（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 48-SSOP
包裝： 管件
產(chǎn)品目錄頁(yè)面： 1080 (CN2011-ZH PDF)
配用： 576-1627-ND - BOARD EVALUATION FOR KSZ8721BMC
576-1626-ND - BOARD EVALUATION FOR KSZ8721BL
其它名稱： 576-1027
March 2006
13
M9999-030106
KS8721B/BT
Micrel, Inc.
Collision: Whenever the line state is half-duplex and the transmitter and receiver are active at the same time, the KS8721B/
BT asserts its collision signal, which is asynchronous to any clock.
RMII (Reduced MII) Data Interface
RMII interface species a low pin count (Reduced) Media Independent Interface (RMII) intended for use between Ethernet
PHYs and Switch or Repeater ASICs. It is fully compliant with IEEE 802.3u [2].
This interface has the following characteristics:
It is capable of supporting 10Mbps and 100Mbps data rates.
A single clock reference is sourced from the MAC to PHY (or from an external source).
It provides independent 2-bit wide (di-bit) transmit and receive data paths.
It uses TTL signal levels, compatible with common digital CMOS ASIC processes.
RMII Signal Denition
Direction
Signal Name
(w/ respect to the PHY)
(w/ respect to the MAC)
Use
REF_CLK
Input
Input or Output
Synchronous clock reference for receive, transmit and
control interface
CRS_DV
Output
Input
Carrier Sense/Receive Data Valid
RXD[1:0]
Output
Input
Receive Data
TX_EN
Input
Output
Transit Enable
TXD[1:0]
Input
Output
Transit Data
RX_ER
Output
Input (Not Required)
Receive Error
Note 1. Unused MII signals, TXD[3:2], TXER need to tie to GND when RMII is using.
Reference Clock (REF_CLK)
REF_CLK is a continuous 50MHz clock that provides the timing reference for CRS_DV, RXD[1:0], TX_EN, TXD[1:0], and
RX_E. REF_CLK is sourced by the MAC or an external source. Switch implementations may choose to provide REF_CLK
as an input or an output depending on whether they provide a REF_CLK output or rely on an external clock distribution
device. Each PHY device shall have an input corresponding to this clock but may use a single clock input for multiple PHYs
implemented on a single IC.
Carrier Sense/Receive Data Valid (CRS_DV)
CRS_DV is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode. That is, in
10BASE-T mode, when squelch is passed or in 100BASE-X mode when 2 non-contiguous zeroes in 10 bits are detected
carrier is said to be detected.
Loss of carrier shall result in the de-assertion of CRS_DV synchronous to REF_CLK. So long as carrier criteria are being
met, CRS_DV shall remain asserted continuously from the rst recovered di-bit of the frame through the nal recovered di-
bit and shall be negated prior to the rst REF_CLK that follows the nal di-bit.
The data on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchro-
nous relative to REF_CLK, the data on RXD[1:0] shall be “00” until proper receive signal decoding takes place (see denition
of RXD[1:0] behavior).
Receive Data [1:0] (RXD[1:0])
RXD[1:0] shall transition synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0] transfers
two bits of recovered data from the PHY. In some cases (e.g. before data recovery or during error conditions) a pre-deter-
mined value for RXD[1:0] is transferred instead of recovered data. RXD[1:0] shall be “00” to indicate idle when CRS_DV is
de-asserted. Values of RXD[1:0] other than “00” when CRS_DV is de-asserted are reserved for out-of-band signalling (to
be dened). Values other than “00” on RXD[1:0] while CRS_DV is de-asserted shall be ignored by the MAC/repeater. Upon
assertion of CRS_DV, the PHY shall ensure that RXD[1:0]=00 until proper receive decoding takes place.
Transmit Enable (TX_EN)
Transmit Enable TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] on the RMII for trans-mission. TX_EN shall
be asserted synchronously with the rst nibble of the preamble and shall remain asserted while all di-bits to be transmitted
are presented to the RMII. TX_EN shall be negated prior to the rst REF_CLK following the nal di-bit of a frame. TX_EN
shall transition synchronously with respect to REF_CLK.
Direction
REF_CLK
Input
Input or Output
Synchronous clock reference for receive, transmit and
control interface
CRS_DV
Output
Input
Carrier Sense/Receive Data Valid
RXD[1:0]
Output
Input
Receive Data
TX_EN
Input
Output
Transit Enable
TXD[1:0]
Input
Output
Transit Data
RX_ER
Output
Input (Not Required)
Receive Error
Direction
(w/ respect to the PHY)
(w/ respect to the MAC)
REF_CLK
Input
Input or Output
Synchronous clock reference for receive, transmit and
control interface
CRS_DV
Output
Input
Carrier Sense/Receive Data Valid
RXD[1:0]
Output
Input
Receive Data
TX_EN
Input
Output
Transit Enable
TXD[1:0]
Input
Output
Transit Data
RX_ER
Output
Input (Not Required)
Receive Error
Use
REF_CLK
Input
Input or Output
Synchronous clock reference for receive, transmit and
control interface
CRS_DV
Output
Input
Carrier Sense/Receive Data Valid
RXD[1:0]
Output
Input
Receive Data
TX_EN
Input
Output
Transit Enable
TXD[1:0]
Input
Output
Transit Data
RX_ER
Output
Input (Not Required)
Receive Error
REF_CLK
Input
Input or Output
Synchronous clock reference for receive, transmit and
Signal Name
REF_CLK
Input
Input or Output
Synchronous clock reference for receive, transmit and
control interface
CRS_DV
Output
Input
Carrier Sense/Receive Data Valid
RXD[1:0]
Output
Input
Receive Data
TX_EN
Input
Output
Transit Enable
TXD[1:0]
Input
Output
Transit Data
RX_ER
Output
Input (Not Required)
Receive Error
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