參數(shù)資料
型號: KSZ8051MNL-EVAL
廠商: Micrel Inc
文件頁數(shù): 14/59頁
文件大小: 0K
描述: BOARD EVALUATION FOR KSZ8051MNL
標準包裝: 1
主要目的: 接口,以太網(wǎng) PHY
嵌入式:
已用 IC / 零件: KSZ8051MNL
已供物品:
相關(guān)產(chǎn)品: 576-3845-ND - TXRX PHY 10/T100 3.3V 32QFN
576-3777-6-ND - TXRX PHY 10/T100 3.3V MII 32-QFN
576-3777-1-ND - TXRX PHY 10/T100 3.3V MII 32-QFN
576-3777-2-ND - TXRX PHY 10/T100 3.3V MII 32-QFN
576-3732-ND - TXRX PHY 10/T100 3.3V MII 32-QFN
其它名稱: 576-3865
Micrel, Inc.
KSZ8051MNL/RNL
July 2010
21
M9999-070910-1.0
Figure 1. Auto-Negotiation Flow Chart
MII Data Interface (KSZ8051MNL only)
The Media Independent Interface (MII) is compliant with the IEEE 802.3 Specification. It provides a common interface
between MII PHYs and MACs, and has the following key characteristics:
Pin count is 15 pins (6 pins for data transmission, 7 pins for data reception, and 2 pins for carrier and collision
indication).
10Mbps and 100Mbps data rates are supported at both half and full duplex.
Data transmission and reception are independent and belong to separate signal groups.
Transmit data and receive data are each 4-bit wide, a nibble.
By default, the KSZ8051MNL is configured to MII mode after it is powered up or hardware reset with the following:
A 25MHz crystal connected to XI, XO (pins 9, 8), or an external 25MHz clock source (oscillator) connected to XI.
The CONFIG[2:0] strapping pins (pins 18, 29, 28) set to ‘000’ (default setting).
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