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    參數(shù)資料
    型號: KSZ8041MLL TR
    廠商: Micrel Inc
    文件頁數(shù): 11/65頁
    文件大?。?/td> 0K
    描述: TXRX 10/100 3.3V PHY MII 48LQFP
    標準包裝: 1,000
    類型: 收發(fā)器
    驅(qū)動器/接收器數(shù): 1/1
    規(guī)程: MII
    電源電壓: 3.135 V ~ 3.465 V
    安裝類型: 表面貼裝
    封裝/外殼: 48-TQFP
    供應商設備封裝: 48-TQFP(7x7)
    包裝: 帶卷 (TR)
    Micrel, Inc.
    KSZ8041TL/FTL/MLL
    December 2009
    19
    M9999-120909-1.2
    Pin Number
    Pin Name
    Type
    (1)
    Pin Function
    27
    RXDV /
    CONFIG2
    Ipd/O
    MII Mode:
    Receive Data Valid Output /
    Config. Mode:
    The pull-up/pull-down value is latched as CONFIG2 during
    power-up / reset. See “Strapping Options” section for details.
    28
    RXC
    O
    MII Receive Clock Output
    29
    RXER /
    ISO
    Ipd/O
    MII Mode:
    Receive Error Output /
    Config. Mode:
    The pull-up/pull-down value is latched as ISOLATE during
    power-up / reset. See “Strapping Options” section for details.
    30
    GND
    Gnd
    Ground
    31
    VDD_1.8
    P
    1.8V digital VDD
    32
    INTRP
    Opu
    Interrupt Output: Programmable Interrupt Output
    Register 1Bh is the Interrupt Control/Status Register for programming the
    interrupt conditions and reading the interrupt status. Register 1Fh bit 9 sets the
    interrupt output to active low (default) or active high.
    33
    TXC
    I/O
    MII Transmit Clock Output
    34
    TXEN
    I
    MII Transmit Enable Input
    35
    TXD0
    I
    MII Transmit Data Input[0]
    (3)
    36
    TXD1
    I
    MII Transmit Data Input[1]
    (3)
    37
    GND
    Gnd
    Ground
    38
    TXD2
    I
    MII Transmit Data Input[2]
    (3)
    /
    39
    TXD3
    I
    MII Transmit Data Input[3]
    (3)
    /
    40
    COL /
    CONFIG0
    Ipd/O
    MII Mode:
    Collision Detect Output /
    Config. Mode:
    The pull-up/pull-down value is latched as CONFIG0 during
    power-up / reset. See “Strapping Options” section for details.
    41
    CRS /
    CONFIG1
    Ipd/O
    MII Mode:
    Carrier Sense Output /
    Config. Mode:
    The pull-up/pull-down value is latched as CONFIG1 during
    power-up / reset. See “Strapping Options” section for details.
    42
    LED0 /
    NWAYEN
    Ipu/O
    LED Output:
    Programmable LED0 Output /
    Config. Mode:
    Latched as Auto-Negotiation Enable (register 0h, bit 12)
    during power-up / reset. See “Strapping Options” section for
    details.
    The LED0 pin is programmable via register 1Eh bits [15:14], and is defined as
    follows.
    LED mode = [00]
    Link/Activity
    Pin State
    LED Definition
    No Link
    H
    OFF
    Link
    L
    ON
    Activity
    Toggle
    Blinking
    LED mode = [01]
    Link
    Pin State
    LED Definition
    No Link
    H
    OFF
    Link
    L
    ON
    LED mode = [10]
    Reserved
    LED mode = [11]
    Reserved
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