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參數(shù)資料
型號(hào)： KS8995XA
廠商： Micrel Inc
文件頁(yè)數(shù)： 6/51頁(yè)
文件大?。?/td> 0K
描述： IC SWITCH 10/100 5PORT 128PQFP
標(biāo)準(zhǔn)包裝： 66
系列： *
類(lèi)型： *
應(yīng)用： *
安裝類(lèi)型： 表面貼裝
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-PQFP（14x20）
包裝： 散裝
配用： 576-1604-ND - EVAL KIT EXPERIMENTAL KS8995XA
KS8995XA
Micrel, Inc.
M9999-051305
14
May 2005
Pin Number
Pin Name
Type(1)
Port
Pin Function(2)
96
LED3-2
Ipu/O
3
LED indicator 2.
95
LED4-0
Ipu/O
4
LED indicator 0.
94
LED4-1
Ipu/O
4
LED indicator 1.
93
LED4-2
Ipu/O
4
LED indicator 2.
92
LED5-0
Ipu/O
5
LED indicator 0.
91
LED5-1
Ipu/O
5
LED indicator 1. Strap option: PU (default): enable PHY MII I/F
Pd: tristate all PHY MII output. See “Pin# 86 SCONF1.”
90
LED5-2
Ipu/O
5
LED indicator 2. Aging setup. See “Aging” section.
107
MDC
Ipu
All
Switch or PHY[5] MII management data clock.
108
MDIO
Ipu/O
All
Switch or PHY[5] MII management data I/O.
45
NC / MUX1
I
No connect. Factory test pin.
46
NC / MUX2
I
No connect. Factory test pin.
68
PCOL
Ipd/O
5
PHY[5] MII collision detect/ Force flow control. See “Register 18.”
67
PCRS
Ipd/O
5
PHY[5] MII carrier sense/Force duplex mode. See “Register 28.”
60
PMRXC
O
5
PHY[5] MII receive clock. PHY mode MII.
65
PMRXD0
Ipd/O
5
PHY[5] MII receive bit 0. Strap option: PD (default) = disable
aggressive back-off algorithm in half-duplex mode; PU = enable for
performance enhancement.
64
PMRXD1
Ipd/O
5
PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive
collision packets; PU = does not drop excessive collision packets.
63
PMRXD2
Ipd/O
5
PHY[5] MII receive bit 2. Strap option: PD (default) = disable back
pressure; PU = enable back pressure.
62
PMRXD3
Ipd/O
5
PHY[5] MII receive bit 3. Strap option: PD (default) = enable flow
control; PU = disable flow control.
61
PMRXDV
Ipd/O
5
PHY[5] MII receive data valid.
66
PMRXER
Ipd/O
5
PHY[5] MII receive error. Strap option: PD (default) = packet size 1518/
1522 bytes; PU = 1536 bytes.
57
PMTXC
O
5
PHY[5] MII transmit clock. PHY mode MII.
55
PMTXD0
Ipd
5
PHY[5] MII transmit bit 0.
54
PMTXD1
Ipd
5
PHY[5] MII transmit bit 1.
53
PMTXD2
Ipd
5
PHY[5] MII transmit bit 2.
52
PMTXD3
Ipd
5
PHY[5] MII transmit bit 3.
51
PMTXEN
Ipd
5
PHY[5] MII transmit enable.
56
PMTXER
Ipd
5
PHY[5] MII transmit error.
114
PS0
Ipd
No connect or pull down.
113
PS1
Ipd
No connect or pull down.
Notes:
1. P = Power supply.
I = Input.
O = Output.
I/O = Bidirectional.
Gnd = Ground.
Ipu = Input w/internal pull-up.
Ipd = Input w/internal pull-down.
Ipd/O = Input w/internal pull-down during reset, output pin otherwise.
Ipu/O = Input w/internal pull-up during reset, output pin otherwise.
2. PU = Strap pin pull-up.
PD = Strap pull-down.
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