KS8695P Micrel Switch Engine (continued) Supports 802.1Q tag-based VLAN and port-based VLAN Supports 8.2,1" />
參數(shù)資料
型號(hào)： KS8695P-EVAL
廠商： Micrel Inc
文件頁(yè)數(shù)： 8/40頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL EXPERIMENT KS8695P
標(biāo)準(zhǔn)包裝： 1
其它名稱： 576-1002
M9999-081805
16
August 2005
KS8695P
Micrel
Switch Engine (continued)
Supports 802.1Q tag-based VLAN and port-based VLAN
Supports 8.2,1p-based priority, DiffServ priority, and post-based priority
Integrated address look-up engine, supports 1K absolute MAC addresses
Automatic address learning, address aging, and address migration
Broadcast storm protection
Full-duplex IEEE 802.3x ow control
Half-duplex back pressure ow control
Supports IGMP snooping
Spanning Tree Protocol support
Advanced Memory Controller Features
Supports glueless connection to two banks of ROM/SRAM/FLASH memory with programmable 8/16/32 bit data bus
and programmable access timing
Supports glueless connection to two SDRAM banks with programmable 8/16/32-bit data bus and programmable
RAS/CAS latency
Supports three external I/O banks with programmable 8/16/32-bit data bus and programmable access timing
Programmable system clock speed for power management
Automatic address line mapping for 8/16/32-bit accesses on Flash, ROM, SRAM, and SDRAM interfaces
Direct Memory Access (DMA) Engines
Independent MAC DMA engine with programmable burst mode for WAN port
Independent MAC DMA engine with programmable burst mode for LAN ports
Supports little-endian byte ordering for memory buffers and descriptors
Contains large independent receive and transmit FIFOs (3KB receive/3KB transmit) for back-to-back packet receive,
and guaranteed no under-run packet transmit
Data alignment logic and scatter gather capability
Protocol Engine/XceleRouter Technology
Supports IPv4 IP header/TCP/UDP packet checksum generation for host CPU ofoading
Supports IPv4 packet ltering based on checksum errors
Network Interface
Features ve MAC units and ve PHY units
Supports 10BASE-T and 100BASE-TX on all LAN ports and one WAN port. Also supports 100BASE-FX on the WAN
port and on one LAN port
Supports automatic CRC generation and checking
Supports automatic error packet discard
Supports IEEE 802.3 auto-negotiation algorithm of full-duplex and half-duplex operation for 10Mbps and 100Mbps
Supports full-/half-duplex operation on PHY interfaces
Fully compliant with IEEE 802.3 Ethernet standards
IEEE 802.3 full-duplex ow control and half-duplex backpressure collision ow control
Supports MDI/MDI-X auto-crossover
Peripherals
Twenty-eight interrupt sources, including four external interrupt sources
Normal or fast interrupt mode (IRQ, FIQ) supported
Prioritized interrupt handling
Sixteen programmable general purpose I/O. Pins individually congurable to input, output, or I/O mode for dedicated
signals.
Two programmable 32-bit timers with watchdog timer capability
High-speed UART interface up to 115kbps
Other Features
Integrated PLL to generate CPU and system clocks
JTAG development interface for ICE connection
19mm x 19mm 289-pin PBGA
1.8V CMOS for core and 3.3V for I/O
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