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參數(shù)資料
| 型號： | KS8695P-EVAL |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 19/40頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL EXPERIMENT KS8695P |
| 標準包裝： | 1 |
| 其它名稱： | 576-1002 |
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August 2005
26
M9999-081805
KS8695P
Micrel
General Purpose I/O Pins (continued)
Pin
Name
I/O Type(1)
Description
D4
PCLK
I
PCI bus clock.This signal provides the timing for the PCI bus transactions. This signal
is used to drive the PCI bus interface and the internal PCI logic. All PCI bus signals
are sampled on the rising edges of the PCLK. PCLK can operate from 20MHz to
33MHz. For host mode, use PCLKOUT0 signal to drive this input. In guest mode,
use the system PCI clock to drive this input.
C2
GNT3N
O
PCI bus grant 3. Active low. In host bridge mode, this is an output signal from the
internal PCI arbiter to grant PCI bus access to the device connected to REQ3N. In
guest bridge mode, this signal is reserved.
C3
GNT2N
O
PCI bus grant 2. Active low. In host bridge mode, this is an output signal from the
internal PCI arbiter to grant PCI bus access to the device connected to REQ2N. In
guest bridge mode, this signal is reserved.
C4
GNT1N
O
PCI bus grant 1. Active low. In host bridge mode, this is an output signal from the
internal PCI arbiter to grant PCI bus access to the device connected to REQ1N. In
guest bridge mode, this signal is an output to indicate that the KS8695P is requesting
to access the PCI bus as a PCI master. In guest bridge mode, this is basically the
KS8695P’s request output.
B2
REQ3N
I
PCI bus request 3. Active low. In host bridge mode, this is an input signal from the
external PCI device to request PCI bus access. In guest bridge mode, this signal is
reserved.
B3
REQ2N
I
PCI bus request 2. Active low. In host bridge mode, this is an input signal from the
external PCI device to request PCI bus access.In guest bridge mode, this signal is
reserved.
B4
REQ1N
I
PCI bus request 1. Active low. In host bridge mode, this is an input signal from the
external PCI device to request PCI bus access. In guest bridge mode, this is an input
signal from an external PCI bus arbiter granting access to the bus. In guest bridge,
this is basically the KS8695P's grant input.
A4
PAD31
I/O
32-Bit PCI address and data. PCI bus transactions consist of an address
D5
PAD30
phase followed by one or more data phases. Address and data signals are multi-
B5
PAD29
plexed on the same pins. For a PCI write transaction, the source of the data is the
C5
PAD28
KS8695P. For a PCI read transaction, the data source is the target. The
A5
PAD27
KS8695P supports both read and write burst transactions. In the case of a read
D6
PAD26
transaction, a special data turn around cycle is needed between the address phase
B6
PAD25
and the data phase(s).
C6
PAD24
B7
PAD23
C7
PAD22
A7
PAD21
D8
PAD20
B8
PAD19
D9
PAD18
A8
PAD17
C9
PAD16
D12
PAD15
B12
PAD14
C12
PAD13
A12
PAD12
D13
PAD11
B13
PAD10
C13
PAD9
A13
PAD8
B14
PAD7
C14
PAD6
A14
PAD5
D15
PAD4
B15
PAD3
Note:
1. I = Input.
O = Output.
I/O = Bidirectional.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KS8695PI | 功能描述:IC ARM9 W/MMU 5PORT 289-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| KS8695P-MDP-EVAL | 功能描述:EVAL KIT EXPERIMENTAL KS8695PMPD RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- 主要目的:電源管理，電池充電器 嵌入式:否 已用 IC / 零件:MAX8903A 主要屬性:1 芯鋰離子電池 次要屬性:狀態(tài) LED 已供物品:板 |
| KS8695P-MMB-EVAL | 功能描述:BOARD EVAL MULTIMEDIA KS8695P RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- 主要目的:電源管理，電池充電器 嵌入式:否 已用 IC / 零件:MAX8903A 主要屬性:1 芯鋰離子電池 次要屬性:狀態(tài) LED 已供物品:板 |
| KS8695PX | 功能描述:IC SWITCH 10/100 1PORT 289PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| KS8695PXA3 | 功能描述:IC ARM9 W/MMU 5PORT 289-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
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