Micrel May 2005 – SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE KS8001 MICREL CONFIDENTIAL. DO NOT DISTRIBUTE. 9 Pin" />
參數(shù)資料
型號(hào)： KS8001LI
廠(chǎng)商： Micrel Inc
文件頁(yè)數(shù)： 44/44頁(yè)
文件大?。?/td> 0K
描述： TXRX 10/100 LINKMD 3.3V 48-LQFP
標(biāo)準(zhǔn)包裝： 250
類(lèi)型： 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 1/1
規(guī)程： MII，RMII，SMII
電源電壓： 3.14 V ~ 3.47 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 管件
配用： KS8001L-EVAL-ND - EVAL KIT EXPERIMENTAL KS8001L
KS8001
Micrel
May 2005 – SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE
KS8001
MICREL CONFIDENTIAL. DO NOT DISTRIBUTE.
9
Pin Number
Pin Name
Type
(Note 1)
Pin Function
36
GND
Gnd
Ground
37
REXT
I
External resistor (6.65K
) connects to REXT and GNDRX
38
VDDRCV
Pwr
Analog 3.3 V power supply (See “Circuit design ref for power supply”
section for details)
39
GND
Gnd
Ground
40
TX-
O
Transmit Outputs
Differential transmit output for 100BASE-TX/FX or 10BASE-T
41
TX+
O
Transmit Outputs
Differential transmit output for FX, 100BASE-TX/FX or 10BASE-T
42
NC
No Connect
43
NC
No Connect
44
GND
Gnd
Ground
45
XO
O
XTAL feedback
Used with XI for Xtal application.
46
XI
I
Crystal Oscillator Input
Input for a crystal or an external 25 MHz clock
47
VDDPLL
Pwr
Analog PLL 1.8 V power supply
48
RST#
Ipu
Chip Reset
Active low, minimum of 50 us pulse is required
Note 1:
Pwr = power supply;
Gnd = ground;
I = input;
O = output;
I/O = bi-directional
Ipu = input w/ internal pull up;
Ipd = input w/ internal pull down;
Ipu/O = input w/ internal pull up during
reset, output pin otherwise;
Ipd/O = input w/ internal pull down during
reset, output pin otherwise;
PD = strap pull down;
PU = strap pull up;
Note 2:
MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD [3..0]
presents valid data to MAC through the MII. RXD [3..0] is invalid when RXDV is de-asserted.
Note 3:
RMII Rx Mode: The RXD[1..0] bits are synchronous with REF_CLK. For each clock period in which
CRS_DV is asserted, two bits of recovered data are sent from the PHY.
Note 4:
SMII Rx Mode: Receive data and control information are sent in 10 bit segments. In 100MBit mode, each
segment represents a new byte of data. In 10MBit mode, each segment is repeated ten times; therefore,
every ten segments represents a new byte of data. The MAC can sample any one of every 10 segments in
10MBit mode.
Note 5:
MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD [3..0]
presents valid data from the MAC through the MII. TXD [3..0] has no effect when TXEN is de-asserted.
Note 6:
RMII Tx Mode: The TXD[1..0] bits are synchronous with REF_CLK. For each clock period in which TX_EN
is asserted, two bits of recovered data are recovered by the PHY.
Note 7:
SMII Tx Mode: Transmit data and control information are received in 10 bit segments. In 100MBit mode,
each segment represents a new byte of data. In 10MBit mode, each segment is repeated ten times;
therefore, every ten segments represents a new byte of data. The PHY can sample any one of every 10
segments in 10MBit mode.
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