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參數(shù)資料
| 型號： | KS57C0004 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 4-BIT CMOS Microcontroller(4位微控制器) |
| 中文描述： | 4位CMOS微控制器（4位微控制器） |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 34K |
| 代理商： | KS57C0004 |
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
ELECTRONICS
S
MSUNG
2–3
September 1996
Table 1. KS57C0002/0004 Pin Descriptions
Pin Name
Pin Type
Description
Number
Share Pin
P0.0
P0.1
P0.2
I/O
3-bit I/O port. 1-bit or 3-bit read/write and test is
possible. Pull-up resistors are assignable to input pins
by software and are automatically disabled for output
pins. Pins are individually configurable as input or
output.
2-bit input port. 1-bit or 2-bit read and test is possible.
Pull-up resistors are assignable by software.
4-bit input port. 1-bit or 4-bit read and test is possible.
1
2
3
SCK
SO
SI
P1.0
P1.1
P2.0–P2.3
I
4
5
INT0
INT1
I
6–9
CIN0–CIN3
P3.0
P3.1
P3.2
P4.0–P4.3
P5.0–P5.3
I/O
Same as port 0
10
11
12
TCL0
TCLO0
CLO
—
I/O
4-bit I/O ports.
1-, 4-, or 8-bit read/write and test is possible.
Pins are individually configurable as input or output.
Ports can be configurable as n-channel open-drain by
mask option (maximum 9V).
4-bit I/O port.
1-bit or 4-bit read/write and test is possible.
Pull-up resistors are assignable to input pins by
software and are automatically disabled for output
pins. Pins individually configurable as input or output.
External interrupts with rising/falling edge detection
18–21
22–25
P6.0
P6.1
P6.2
P6.3
I/O
26
27
28
29
KS0
KS1
KS2
BUZ
INT0
I
4
P1.0
INT1
I
External interrupts with rising/falling edge detection
5
P1.1
CIN0–CIN3
I
4-channel comparator input.
CIN0–CIN2: comparator input only.
CIN3: comparator input or external reference input
Serial interface clock signal
6–9
P2.0–P2.3
SCK
SO
I/O
1
P0.0
I/O
Serial data output
2
P0.1
SI
I/O
Serial data input
3
P0.2
TCL0
I/O
External clock input for timer/counter
10
P3.0
TCLO0
I/O
Timer/counter clock output
11
P3.1
CLO
I/O
CPU clock output
12
P3.2
BUZ
I/O
2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at
4.19 MHz for buzzer sound
Quasi-interrupt input with falling edge detection
29
P6.3
KS0–KS2
I/O
26–28
P6.0–P6.2
V
DD
V
SS
—
Main power supply
30
—
—
Ground
15
—
RESET
TEST
I
Reset signal
13
—
I
Test signal input (must be connected to V
SS
)
Crystal, ceramic, or RC oscillator signal for system
clock
14
—
X
in
, X
out
—
16, 17
—
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KS57C01502 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The KS57C01502/C01504 single-chip CMOS microcontroller has been designed for high-performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Arr |
| KS57C01504 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The KS57C01502/C01504 single-chip CMOS microcontroller has been designed for high-performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Arr |
| KS57C0301 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The KS57C0301/0302 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core. |
| KS57C0302 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The KS57C0301/0302 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core. |
| KS57C0404 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The KS57C0404/C0408 single-chip CMOS microcontroller has been designed for very high-performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung |
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