參數(shù)資料
型號: KS16112
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: CAP 33PF 50V 5% NPO(C0G) SMD-0603 TR-7-PA
中文描述: 14400分之9600基點傳真調(diào)制解調(diào)器
文件頁數(shù): 29/69頁
文件大?。?/td> 513K
代理商: KS16112
KS16112/4
9600/14400 bps FAX MODEM
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29
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A bit mask function is performed by this byte on the register specified by INTADR for the programmable
interrupt. The INTML bit determines whether a logical AND or a logical OR masking operation is performed
with the contents of the register specified by INTADR and the contents of INTMSK. Note that ITRIG places
additional triggering requirements which must also be met in order for IRQ to be asserted by the modem.
Additionally, programmable interrupts must be enabled ( PINTE set ) and PIRQ must have been reset by the
host prior to the occurrence of the interrupt condition in order for IRQ to be asserted by the modem.
ITRIG places triggering polarity requirements on the programmable interrupt which must be met in order for
the modem to assert IRQ. The four possible ITRIG settings and their corresponding function are described
below.
Interrupt Triggering
0A : 6 -7 ( 0 )
ITRIG
INTMSK
Interrupt Bit Mask
0B : 0 - 7 ( 0 )
During HDLC parallel mode data transmission ( HDLCE and PDME are set ) the host microprocessor must
load DBFR with consecutive transmit data bytes within eight bit times of each other. If more than eight bit
times elapse between transmit data bytes being written into DBFR, an underrun condition is detected by the
modem and is indicated by the ORUR and ABORT bits being set. When an underrun condition occurs, the
modem clamps the transmit data to ones. The clamping of transmit data will continue until the host
microprocessor resets the ABORT bit. When the host microprocessor resets the ABORT bit, the modem will
complete the transmission of the current group of eight binary ones and will then proceed to start the
transmission of the next frame if BA2 has been reset ( the host reading or writing DBFR causes BA2 to
reset ). Otherwise, the modem will transmit continuous HDLC flags.
In the receive mode, the modem indicates an overrun condition by setting ORUR. An overrun condition
occurs when the host microprocessor fails to read the received data in DBFR before it is overwritten by the
next received byte. The host must reset the ORUR bit before the next received data overrun condition can
be indicated by the modem setting ORUR.
ORUR
Overrun / Underrun
09 : 7 ( - )
ITRIG (Bin)
Description
Continuous interrupt when interrupt condition
Interrupt when interrupt condition from false to true
Interrupt when interrupt condition from true to false
Interrupt when any change in interrupt condition
00
01
10
11
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