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參數(shù)資料
| 型號： | KS0164 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Multimedia Audio(波表合成芯片) |
| 中文描述： | 多媒體音響（波表合成芯片） |
| 文件頁數(shù)： | 5/18頁 |
| 文件大?。?/td> | 83K |
| 代理商： | KS0164 |
KS0164 MULTIMEDIA AUDIO
5/
19
PIN DESCRIPTION
Pin Name
Pin #
Type
Description
HOST PC INTERFACE
HA9-0
3-12
I
Host Address Bits 9-0. These are the low 10 bits of the Host PC
address bus, which are decoded to control access the MPU-401. For
IBM PC application, these pins should be connected directly to A[9:0].
Alternatively, these pins may be tied to GND, and a fully qualified chip
select signal may be connected to the CSL* pin instead.
Host Address Enable. This is the Host PC address decode enable.
When Low, this signal enables the on-chip address decoder to decode
HA[9:0], according to the base address selected by the BAS[1:0]
signals. In this mode, the CSL* may be used instead. In this mode,
only HA[3:0] will be decoded. For IBM-PC applications, this pin should
be connected directly to AEN*.
Base Address Select. These signals select the base address for the
MPU-401 emulation as follows:
00b => 320-321H
01b => 330-331H
10b => 340-341H
11b => 350-351H
Chip Select. For use at non-standard I/O addresses, or in applications
where a chip select signal is available, HAEN* may be tied high, and
the external chip select connected to CSL* instead. In this mode, only
HA[3:0] are decoded on-chip.
Buffered Host PC Data Bus Bits [0:7].
Host I/O Read. This is the Host PC I/O read enable. The chip will only
drive the HD[7:0] bus when a valid address decode is present, as
determined by the HAEN*, BAS[1:0], and CSL* signals, and HIOR* is
low.
Host I/O Write. This is the Host PC I/O write strobe. Data is written to
internal registers on the rising edge of this signal.
Host PC Reset. The active polarity of this signal is determined by the
HRSTPOL pin. For IBM PC application, this pin should be connected
directly to the PC-bus RSTDRV signal. For daughter card applications,
connect this pin to the reset signal from the host board.
HRST polarity select. This signal selects the active polarity for the
HRST signal. When this pin is tied low, HRST will be active low.
Host PC Data Bus Buffer Enable. This output controls the enable to the
74LS245 which buffers the Host PC data bus. This pin is driven low
any time the MPU-401 is addressed for an I/O access.
Host MPU-401 Interrupt. This is a active high interrupt output from the
MPU-401. It should be connected to one of the host IRQ lines,
normally IRQ2.
HAEN*
16
I
BAS[1:0]
87,88
I
CSL*
89
I
HD[7:0]
HIOR*
19-26
13
I/O
I
HIOW*
14
I
HRST
1
I
HRSTPOL
90
I
HDBEN*
15
O
HINT
2
O
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