參數(shù)資料
型號(hào)： KS0123
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： DIGITAL VIDEO ENCODER
中文描述： 數(shù)字視頻編碼器
文件頁(yè)數(shù)： 22/44頁(yè)
文件大小： 456K
代理商： KS0123
KS0123 Data Sheet
MULTIMEDIA VIDEO
PAGE 22 OF 44
Modified on May/04/2000
Serial Host Interface
The internal control registers of the encoder are read and written via a two wire serial port. The two wire port
consists of a serial I/O data line (SDA) and a clock (SCL) input. Each of the SDA and SCL line is connected to
+VDD with a pull-up resistor. The data on the SDA line must be stable when the clock (SCL) is high. Data can only
change while SCL is low. Transitions on SDA while SCL is high indicate start (high to low transition) and stop (low
to high) conditions. When both lines are high, the bus is considered to be free.
Communication consists of five parts: the START signal, slave address transmission, (register address
transmission), data transfer, and the STOP signal. When the bus is free, a master initiates communication by
sending a start signal (high to low of SDA while SCL is high). The first byte transferred after the start signal is a
seven bit long slave address followed by the eighth R/W bit. The R/W bit indicates the direction of data transfer
(high = read). If the slave address matches that of the encoder (set with pins SA1 and SA2), the encoder will
acknowledge by pulling SDA low during the 9th clock. The bytes following the slave address are the data to or from
the encoder. Each byte is 8 bits long with the MSB transferred first. Each byte is followed by an acknowledge by
the receiving device by pulling the SDA line low during the 9th clock. A stop signal is created when the master
sends a low to high on the SDA line with SCL high. Figure 15 shows the data transfer and acknowledge on the
serial bus.
Figure 15. Serial Bus Timing
S
1
2
7
8
9
1
2
3 8
9
P
ACK
ACK
MSB
SDA
SCL
START CONDITION
STOP CONDITION
acknowledgment
signal from receiver
byte complete,
interrupt in receiver
clock line held low while
interrupts are serviced
acknowledgment
signal from receiver
SERIAL DATA TRANSFER
not acknowledge
acknowledge
8
9
1
2
S
Data output
by transmitter
Data output
by receiver
SCL from
master
START CONDITION
clock pulse for
acknowledgment
ACKNOWLEDGE ON THE SERIAL BUS
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