參數(shù)資料
型號: KMPC870VR80
廠商: Freescale Semiconductor
文件頁數(shù): 66/84頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC 80MHZ 256PBGA
標(biāo)準(zhǔn)包裝: 2
系列: MPC8xx
處理器類型: 32-位 MPC8xx PowerQUICC
速度: 80MHz
電壓: 3.3V
安裝類型: 表面貼裝
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-PBGA(23x23)
包裝: 托盤
MPC875/MPC870 PowerQUICC Hardware Specifications, Rev. 4
Freescale Semiconductor
69
FEC Electrical Characteristics
Figure 66 shows the MII transmit signal timing diagram.
Figure 66. MII Transmit Signal Timing Diagram
15.3
MII Async Inputs Signal Timing (MII_CRS, MII_COL)
Table 33 provides information on the MII async inputs signal timing.
Figure 67 shows the MII asynchronous inputs signal timing diagram.
Figure 67. MII Async Inputs Timing Diagram
15.4
MII Serial Management Channel Timing (MII_MDIO, MII_MDC)
Table 34 provides information on the MII serial management channel signal timing. The FEC functions
correctly with a maximum MDC frequency in excess of 2.5 MHz.
Table 33. MII Async Inputs Signal Timing
Num
Characteristic
Min
Max
Unit
M9
MII_CRS, MII_COL minimum pulse width
1.5
MII_TX_CLK period
Table 34. MII Serial Management Channel Timing
Num
Characteristic
Min
Max
Unit
M10
MII_MDC falling edge to MII_MDIO output invalid (minimum propagation
delay)
0—
ns
M11
MII_MDC falling edge to MII_MDIO output valid (max prop delay)
25
ns
M12
MII_MDIO (input) to MII_MDC rising edge setup
10
ns
M13
MII_MDIO (input) to MII_MDC rising edge hold
0
ns
M14
MII_MDC pulse width high
40%
60%
MII_MDC period
M15
MII_MDC pulse width low
40%
60%
MII_MDC period
M6
MII_TX_CLK (Input)
MII_TXD[3:0] (Outputs)
MII_TX_EN
MII_TX_ER
M5
M7
M8
MII_CRS, MII_COL
M9
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