參數(shù)資料
型號： KMPC860SRCZQ50D4
廠商： Freescale Semiconductor
文件頁數(shù)： 11/78頁
文件大?。?/td> 0K
描述： IC MPU POWERQUICC 50MHZ 357-PBGA
標準包裝： 2
系列： MPC8xx
處理器類型： 32-位 MPC8xx PowerQUICC
速度： 50MHz
電壓： 3.3V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應商設備封裝： 357-PBGA（25x25）
包裝： 托盤
MPC860 PowerQUICC Family Hardware Specifications, Rev. 9
Freescale Semiconductor
19
Bus Signal Timing
B31a
CLKOUT falling edge to CS valid—as
requested by control bit CST1 in the
corresponding word in UPM
7.58
14.33
6.25
13.00
5.00
11.75
3.80
10.54
ns
B31b
CLKOUT rising edge to CS valid—as
requested by control bit CST2 in the
corresponding word in UPM
1.50
8.00
1.50
8.00
1.50
8.00
1.50
8.00
ns
B31c
CLKOUT rising edge to CS valid—as
requested by control bit CST3 in the
corresponding word in UPM
7.58
14.33
6.25
13.00
5.00
11.75
3.80
10.04
ns
B31d
CLKOUT falling edge to CS valid—as
requested by control bit CST1 in the
corresponding word in UPM, EBDF = 1
13.26
17.99
11.28
16.00
9.40
14.13
7.58
12.31
ns
B32
CLKOUT falling edge to BS valid—as
requested by control bit BST4 in the
corresponding word in UPM
1.50
6.00
1.50
6.00
1.50
6.00
1.50
6.00
ns
B32a
CLKOUT falling edge to BS valid—as
requested by control bit BST1 in the
corresponding word in UPM, EBDF = 0
7.58
14.33
6.25
13.00
5.00
11.75
3.80
10.54
ns
B32b
CLKOUT rising edge to BS valid—as
requested by control bit BST2 in the
corresponding word in UPM
1.50
8.00
1.50
8.00
1.50
8.00
1.50
8.00
ns
B32c
CLKOUT rising edge to BS valid—as
requested by control bit BST3 in the
corresponding word in UPM
7.58
14.33
6.25
13.00
5.00
11.75
3.80
10.54
ns
B32d
CLKOUT falling edge to BS valid—as
requested by control bit BST1 in the
corresponding word in UPM, EBDF = 1
13.26
17.99
11.28
16.00
9.40
14.13
7.58
12.31
ns
B33
CLKOUT falling edge to GPL valid—as
requested by control bit GxT4 in the
corresponding word in UPM
1.50
6.00
1.50
6.00
1.50
6.00
1.50
6.00
ns
B33a
CLKOUT rising edge to GPL valid—as
requested by control bit GxT3 in the
corresponding word in UPM
7.58
14.33
6.25
13.00
5.00
11.75
3.80
10.54
ns
B34
A(0:31), BADDR(28:30), and D(0:31) to CS
valid—as requested by control bit CST4 in
the corresponding word in UPM
5.58
—
4.25
—
3.00
—
1.79
—
ns
B34a
A(0:31), BADDR(28:30), and D(0:31) to CS
valid—as requested by control bit CST1 in
the corresponding word in UPM
13.15
—
10.50
—
8.00
—
5.58
—
ns
B34b
A(0:31), BADDR(28:30), and D(0:31) to CS
valid—as requested by control bit CST2 in
the corresponding word in UPM
20.73
—
16.75
—
13.00
—
9.36
—
ns
Table 7. Bus Operation Timings (continued)
Num
Characteristic
33 MHz
40 MHz
50 MHz
66 MHz
Unit
Min
Max
Min
Max
Min
Max
Min
Max
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