參數(shù)資料
型號： KMPC8560PX833LC
廠商： Freescale Semiconductor
文件頁數(shù)： 8/36頁
文件大小： 0K
描述： IC MPU POWERQUICC III 783-FCPBGA
標準包裝： 2
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 833MHz
電壓： 1.2V
安裝類型： 表面貼裝
封裝/外殼： 784-BBGA，F(xiàn)CBGA
供應商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
16
MPC8560 PowerQUICC III
MOTOROLA
Integrated Communications Processor Product Brief
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Boot Sequencer
complex applications with multiprocessor control. The I2C controller consists of a transmitter/receiver unit,
a clocking unit, and a control unit. The I2C unit supports general broadcast mode, and on-chip filtering
rejects spikes on the bus.
3.8
Boot Sequencer
The MPC8560 provides a boot sequencer that uses the I2C interface to access an external serial ROM and
loads the data into the MPC8560’s configuration registers. The boot sequencer is enabled by a configuration
pin sampled at the negation of the MPC8560 hardware reset signal. If enabled, the boot sequencer holds the
MPC8560 processor core in reset until the boot sequence is complete. If the boot sequencer is not enabled,
the processor core exits reset and fetches boot code in default configurations.
3.9
Local Bus Controller (LBC)
The MPC8560 local bus controller (LBC) port allows connections with a wide variety of external memories,
DSPs, and ASICs. Three separate state machines share the same external pins and can be programmed
separately to access different types of devices. The general-purpose chip select machine (GPCM) controls
accesses to asynchronous devices using a simple handshake protocol. The user programmable machine
(UPM) can be programmed to interface to synchronous devices or custom ASIC interfaces. The SDRAM
controller provides access to standard SDRAM. Each chip select can be configured so that the associated
chip interface can be controlled by the GPCM, UPM, or SDRAM controller. All may exist in the same
system.
The GPCM provides a flexible asynchronous interface to SRAM, EPROM, FEPROM, ROM, and other
devices such as asynchronous DSP host interfaces and CAMs. Minimal glue logic is required. Handshake
signals can be configured to transition on fractions of the system clock. The GPCM does not support
bursting.
The UPM allows an extremely flexible interface in which the programmer configures each of a set of
general-purpose protocol signals by writing the transition pattern into a memory array. The UPM supports
synchronous and bursting interfaces. It also supports multiplexed addressing so that a simple DRAM
interface can be implemented. The UPM is entirely flexible in order to provide a very high degree of
customization with respect to both asynchronous and burst-synchronous interfaces, which permits glueless
or almost glueless connection to burst SRAM, custom ASIC, and synchronous DSP interfaces.
The LBC provides a synchronous DRAM (SDRAM) machine that supplies the control functions and signals
for glueless connection to JEDEC–compliant SDRAM devices. An internal DLL (delay-locked loop) for
bus clock generation ensures improved data setup margins for board designs. The SDRAM machine can
optimize burst transfers and exploits interleaving to maximize data transfer bandwidth and minimize access
latency. Programmable row and column address multiplexing allows a variety of SDRAM configurations
and sizes to be supported without hardware changes.
3.10 Three-Speed Ethernet Controllers (10/100/1Gb)
The MPC8560 has two on-chip three-speed Ethernet controllers (TSECs). The TSECs incorporate a media
access control sublayer (MAC) that supports 10- and 100-Mbps, and 1-Gbps Ethernet/802.3 networks with
MII, GMII, RGMII, RTBI, and TBI physical interfaces. The TSECs include 2-Kbyte receive and transmit
FIFOs, and DMA functions.
The buffer descriptors are based on the MPC8260 and MPC860T 10/100 programming models.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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