參數(shù)資料
型號(hào): KMPC852TCZT100A
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 34/80頁(yè)
文件大小: 0K
描述: IC MPU PWRQUICC 100MHZ 256PBGA
標(biāo)準(zhǔn)包裝: 2
系列: MPC8xx
處理器類(lèi)型: 32-位 MPC8xx PowerQUICC
速度: 100MHz
電壓: 1.8V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-PBGA(23x23)
包裝: 托盤(pán)
MPC852T PowerQUICC Hardware Specifications, Rev. 4
4
Freescale Semiconductor
Features
Two baud rate generators
— Independent (can be connected toany SCC3/4 or SMC1)
— Allows changes during operation
— Autobaud support option
Two SCCs (serial communication controllers)
— Ethernet/IEEE 802.3 standard optional on SCC3 and SCC4, supporting full 10-Mbps
operation
— HDLC/SDLC
— HDLC bus (implements an HDLC-based local area network (LAN))
— Universal asynchronous receiver transmitter (UART)
— Totally transparent (bit streams)
— Totally transparent (frame-based with optional cyclic redundancy check (CRC))
One SMC (serial management channel)
— UART
One SPI (serial peripheral interface)
— Supports master and slave modes
— Supports multimaster operation on the same bus
PCMCIA interface
— Master (socket) interface, release 2.1 compliant
— Supports one independent PCMCIA socket; 8-memory or I/O windows supported
Debug interface
— Eight comparators: four operate on instruction address, two operate on data address, and two
operate on data
— Supports conditions: =
≠ < >
— Each watchpoint can generate a break point internally
Normal high and normal low power modes to conserve power
1.8 V core and 3.3-V I/O operation with 5-V TTL compatibility. Refer to Table 5 for a listing of
the 5-V tolerant pins.
Figure 1 shows the MPC852T block diagram.
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