參數(shù)資料
型號(hào): KMPC8360EZUALFHA
廠商: Freescale Semiconductor
文件頁數(shù): 7/102頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC II PRO 740TBGA
標(biāo)準(zhǔn)包裝: 2
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 667MHz
電壓: 1.3V
安裝類型: 表面貼裝
封裝/外殼: 740-LBGA
供應(yīng)商設(shè)備封裝: 740-TBGA(37.5x37.5)
包裝: 托盤
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
12
Freescale Semiconductor
Power Sequencing
2.2.1
Power-Up Sequencing
MPC8360E/58E does not require the core supply voltage (VDD and AVDD) and I/O supply voltages (GVDD, LVDD, and OVDD)
to be applied in any particular order. During the power ramp up, before the power supplies are stable and if the I/O voltages are
supplied before the core voltage, there may be a period of time that all input and output pins are actively be driven and cause
contention and excessive current from 3A to 5A. In order to avoid actively driving the I/O pins and to eliminate excessive current
draw, apply the core voltage (VDD) before the I/O voltage (GVDD, LVDD, and OVDD) and assert PORESET before the power
supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal
value before the I/O supplies reach 0.7 V, see this figure.
Figure 5. Power Sequencing Example
I/O voltage supplies (GVDD, LVDD, and OVDD) do not have any ordering requirements with respect to one another.
2.2.2
Power-Down Sequencing
The MPC8360E/58E does not require the core supply voltage and I/O supply voltages to be powered down in any particular
order.
3
Power Characteristics
The estimated typical power dissipation values are shown in these tables.
Table 4. MPC8360E TBGA Core Power Dissipation1
Core
Frequency (MHz)
CSB
Frequency (MHz)
QUICC Engine
Frequency (MHz)
Typical
Maximum
Unit
Notes
266
500
5.0
5.6
W
2, 3, 5
400
266
400
4.5
5.0
W
2, 3, 4
533
266
400
4.8
5.3
W
2, 3, 4
667
333
400
5.8
6.3
W
500
333
500
5.9
6.4
W
I/O Voltage (GVDD, LVDD, OVDD)
Core Voltage (VDD, AVDD)
90%
0.7 V
Time
Voltage
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