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| 型號： | KMPC8358VRAGDGA |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 16/95頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU POWERQUICC II 668-PBGA |
| 標(biāo)準(zhǔn)包裝： | 2 |
| 系列： | MPC83xx |
| 處理器類型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 400MHz |
| 電壓： | 1.2V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 668-BBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 668-PBGA-PGE（29x29） |
| 包裝： | 托盤 |
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MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
Freescale Semiconductor
23
DDR and DDR2 SDRAM
Figure 6 shows the DDR SDRAM output timing for address skew with respect to any MCK.
Figure 6. Timing Diagram for tAOSKEW Measurement
MDQS epilogue end
tDDKHME
–0.6
0.9
ns
7
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs
(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. In the source synchronous mode, MCK/MCK can be shifted in applied cycle increments through the clock control register.
For the skew measurements referenced for tAOSKEW it is assumed that the clock adjustment is set to align the
address/command valid with the rising edge of MCK.
4. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the
ADDR/CMD setup and hold specifications, it is assumed that the clock control register is set to adjust the memory clocks by
applied cycle.
5. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD)
from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control
of the DQSS override bits in the TIMING_CFG_2 register. In source synchronous mode, this will typically be set to the same
delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these two
parameters have been set to the same adjustment value. See the
MPC8360E PowerQUICC II Pro Integrated
Communications Processor Family Reference Manual for a description and understanding of the timing modifications
enabled by use of these bits.
6. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the device.
7. All outputs are referenced to the rising edge of MCK(n) at the pins of the device. Note that tDDKHMP follows the symbol
conventions described in note 1.
8. AC timing values are based on the DDR data rate, which is twice the DDR memory bus frequency.
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications for Source
Synchronous Mode (continued)
At recommended operating conditions with GVDD of (1.8 V or 2.5 V) ± 5%.
Parameter8
Symbol1
Min
Max
Unit
Notes
ADDR/CMD
MCK[n]
tMCK
CMD
NOOP
tAOSKEW(min)
ADDR/CMD
CMD
NOOP
tAOSKEW(max)
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| KMPC8358VVAGDG | 功能描述:微處理器 - MPU 8360 TBGA NOPB RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| KMPC8358VVAGDGA | 功能描述:微處理器 - MPU 8360 TBGA NON-ENC NO-PB RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| KMPC8358ZQAGDDA | 功能描述:微處理器 - MPU 8358 PBGA NON-ENCRP RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| KMPC8358ZQAGDGA | 功能描述:微處理器 - MPU 8358 PBGA NON-ENCRP RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| KMPC8358ZUAGDG | 功能描述:微處理器 - MPU 8360 TBGA NONENCRP RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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