參數(shù)資料
型號(hào): KMPC8358VRAGDDA
廠商: Freescale Semiconductor
文件頁數(shù): 91/95頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC II PRO 668PBGA
標(biāo)準(zhǔn)包裝: 2
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 668-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 668-PBGA-PGE(29x29)
包裝: 托盤
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
Freescale Semiconductor
91
System Design Information
24.5
Output Buffer DC Impedance
The device drivers are characterized over process, voltage, and temperature. For all buses, the driver is a
push-pull single-ended driver type (open drain for I2C).
To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD
or GND. Then, the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 55). The
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals
OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each
other in value. Then, Z0 = (RP + RN)/2.
Figure 55. Driver Impedance Measurement
The value of this resistance and the strength of the driver’s current source can be found by making two
measurements. First, the output voltage is measured while driving logic 1 without an external differential
termination resistor. The measured voltage is V1 = Rsource × Isource. Second, the output voltage is measured
while driving logic 1 with an external precision differential termination resistor of value Rterm. The
measured voltage is V2 = 1/(1/R1 +1/R2)) × Isource. Solving for the output impedance gives Rsource =
Rterm × (V1/V2 – 1). The drive current is then Isource =V1/Rsource.
Table 77 summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD,
nominal OVDD, 105°C.
Table 77. Impedance Characteristics
Impedance
Local Bus, Ethernet, DUART,
Control, Configuration, Power
Management
PCI
DDR DRAM
Symbol
Unit
RN
42 Target
25 Target
20 Target
Z0
W
RP
42 Target
25 Target
20 Target
Z0
W
OVDD
OGND
RP
RN
Pad
Data
SW1
SW2
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