參數(shù)資料
型號(hào)： KMC7447AHX1167NB
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 53/56頁(yè)
文件大?。?/td> 0K
描述： IC MPU RISC 32BIT 1167MHZ 360BGA
標(biāo)準(zhǔn)包裝： 2
系列： MPC74xx
處理器類型： 32-位 MPC74xx PowerPC
速度： 1.167GHZ
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 360-BCBGA，F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝： 360-FCCBGA（25x25）
包裝： 托盤
MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5
6
Freescale Semiconductor
Features
– TLBs are hardware- or software-reloadable (that is, a page table search is performed in
hardware or by system software on a TLB miss).
Efficient data flow
— Although the VR/LSU interface is 128 bits, the L1/L2 bus interface allows up to 256 bits.
— The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the VRs.
— The L2 cache is fully pipelined to provide 256 bits per processor clock cycle to the L1 cache.
— As many as eight outstanding out-of-order cache misses are allowed between the L1 data cache
and the L2 bus.
— As many as 16 out-of-order transactions can be present on the MPX bus.
— Store merging for multiple store misses to the same line. Only coherency action taken
(address-only) for store misses merged to all 32 bytes of a cache block (no data tenure needed).
— Three-entry finished store queue and five-entry completed store queue between the LSU and
the L1 data cache
— Separate additional queues for efficient buffering of outbound data (such as castouts and
write-through stores) from the L1 data cache and L2 cache
Multiprocessing support features include the following:
— Hardware-enforced, MESI cache coherency protocols for data cache
— Load/store with reservation instruction pair for atomic memory references, semaphores, and
other multiprocessor operations
Power and thermal management
— A new dynamic frequency switching (DFS) feature allows processor core frequency to be
halved through software to reduce power consumption.
— The following three power-saving modes are available to the system:
– Nap—Instruction fetching is halted. Only the clocks for the time base, decrementer, and
JTAG logic remain running. The part goes into the doze state to snoop memory operations
on the bus and then back to nap using a QREQ/QACK processor-system handshake
protocol.
– Sleep—Power consumption is further reduced by disabling bus snooping, leaving only the
PLL in a locked and running state. All internal functional units are disabled.
– Deep sleep—When the part is in the sleep state, the system can disable the PLL. The system
can then disable the SYSCLK source for greater system power savings. Power-on reset
procedures for restarting and relocking the PLL must be followed upon exiting the deep
sleep state.
— Instruction cache throttling provides control of instruction fetching to limit device temperature.
— A new temperature diode can determine the temperature of the microprocessor.
— Support for core voltage derating to further reduce power consumption
Performance monitor can be used to help debug system designs and improve software efficiency.
In-system testability and debugging features through JTAG boundary-scan capability
Testability
— LSSD scan design
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