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參數資料
| 型號： | KM718V987 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Kx36 & 512Kx18 Synchronous SRAM |
| 中文描述： | 256Kx36 |
| 文件頁數： | 4/20頁 |
| 文件大小： | 536K |
| 代理商： | KM718V987 |
512Kx36 & 1Mx18 Synchronous SRAM
- 4 -
Rev 1.0
December 1999
KM718V089
KM736V989
PIN CONFIGURATION
(TOP VIEW)
PIN NAME
Note :
1. A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A
0
- A
19
ADV
ADSP
ADSC
CLK
CS
1
CS
2
CS
2
WEx(x=a,b)
OE
GW
BW
ZZ
LBO
Address Inputs
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
32,33,34,35,36,37,42
43,44,45,46,47,48,49
50 80,81,82,99,100
83
84
85
89
98
97
92
93,94
86
88
87
64
31
V
DD
V
SS
N.C.
DQa
0
~ a
7
DQb
0
~ b
7
DQPa, Pb
V
DDQ
V
SSQ
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
Output Power Supply
(3.3V or 2.5V)
Output Ground
15,41,65,91
17,40,67,90
1,2,3,6,7,14,16,25,28,29
30,38,39,51,52,53,56,57
66,75,78,79,95,96
58,59,62,63,68,69,72,73
8,9,12,13,18,19,22,23
74,24
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
N.C.
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
N.C.
DQb
0
DQb
1
V
SSQ
V
DDQ
DQb
2
DQb
3
N.C.
V
DD
N.C.
V
SS
DQb
4
DQb
5
V
DDQ
V
SSQ
DQb
6
DQb
7
DQPb
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
DQPa
DQa
7
DQa
6
V
SSQ
V
DDQ
DQa
5
DQa
4
V
SS
N.C.
V
DD
ZZ
DQa
3
DQa
2
V
DDQ
V
SSQ
DQa
1
DQa
0
N.C.
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
1
9
9
9
9
9
9
9
9
9
9
8
8
8
8
8
8
8
8
A
6
A
7
C
1
C
2
N
N
W
W
C
2
V
D
V
S
C
G
B
O
A
A
A
A
8
8
A
9
5
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
A
1
A
1
A
1
A
1
A
1
A
1
A
1
V
D
V
S
N
N
A
0
A
1
A
2
A
3
A
4
A
5
3
L
A
1
A
1
A
10
KM718V089(1Mx18)
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