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參數(shù)資料
| 型號： | KM68V1002C |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128K x 8 Bit High-Speed CMOS Static RAM(3.3V Operating)(128K x 8位高速CMOS 靜態(tài) RAM) |
| 中文描述： | 128K的× 8位高速CMOS靜態(tài)RAM（3.3V的工作）（128K的× 8位高速的CMOS靜態(tài)RAM）的 |
| 文件頁數(shù)： | 8/9頁 |
| 文件大?。?/td> | 131K |
| 代理商： | KM68V1002C |
KM68V1002C/CL, KM68V1002CI/CLI
CMOS SRAM
PRELIMINARY
Revision 0.0
August 1998
- 8 -
DATA RETENTION CHARACTERISTICS*
(T
A
=0 to 70
°
C
)
NOTE: The above parameters are also guaranteed at industrial temperature range.
* L-Ver only.
Parameter
Symbol
Test Condition
Min.
Typ.
Max.
Unit
V
CC
for Data Retention
V
DR
CS
≥
V
CC
-0.2V
V
CC
=3.0V, CS
≥
V
CC
-0.2V
V
IN
≥
V
CC
-0.2V or V
IN
≤
0.2V
2.0
-
3.6
V
Data Retention Current
I
DR
-
-
0.25
mA
V
CC
=2.0V, CS
≥
V
CC
-0.2V
V
IN
≥
V
CC
-0.2V or V
IN
≤
0.2V
-
-
0.2
Data Retention Set-Up Time
t
SDR
See Data Retention
Wave form(below)
0
-
-
ns
Recovery Time
t
RDR
5
-
-
ms
DATA RETENTION WAVE FORM
V
CC
3.0V
V
IH
V
DR
CS
GND
Data Retention Mode
CS
≥
V
CC
- 0.2V
t
SDR
t
RDR
CS controlled
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