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參數(shù)資料
| 型號： | KM68V1002C |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128K x 8 Bit High-Speed CMOS Static RAM(3.3V Operating)(128K x 8位高速CMOS 靜態(tài) RAM) |
| 中文描述： | 128K的× 8位高速CMOS靜態(tài)RAM（3.3V的工作）（128K的× 8位高速的CMOS靜態(tài)RAM）的 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大小： | 131K |
| 代理商： | KM68V1002C |
KM68V1002C/CL, KM68V1002CI/CLI
CMOS SRAM
PRELIMINARY
Revision 0.0
August 1998
- 5 -
WRITE CYCLE
NOTE: The above parameters are also guaranteed at industrial temperature range.
Parameter
Symbol
KM68V1002C/CL-12
KM68V1002C/CL-15
KM68V1002C/CL-20
Unit
Min
Max
Min
Max
Min
Max
Write Cycle Time
t
WC
12
-
15
-
20
-
ns
Chip Select to End of Write
t
CW
8
-
9
-
10
-
ns
Address Set-up Time
t
AS
0
-
0
-
0
-
ns
Address Valid to End of Write
t
AW
8
-
9
-
10
-
ns
Write Pulse Width(OE High)
t
WP
8
-
9
-
10
-
ns
Write Pulse Width(OE Low)
t
WP1
12
-
15
-
20
-
ns
Write Recovery Time
t
WR
0
-
0
-
0
-
ns
Write to Output High-Z
t
WHZ
0
6
0
7
0
9
ns
Data to Write Time Overlap
t
DW
6
-
7
-
8
-
ns
Data Hold from Write Time
t
DH
0
-
0
-
0
-
ns
End Write to Output Low-Z
t
OW
3
-
3
-
3
-
ns
Address
Data Out
Previous Valid Data
Valid Data
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL
, WE=V
IH
)
t
AA
t
RC
t
OH
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
CS
Address
OE
Data ou
t
t
AA
t
OLZ
t
LZ(4,5)
t
OH
t
OHZ
t
RC
t
OE
t
CO
t
PU
t
PD
Valid Data
t
HZ(3,4,5)
50%
50%
V
CC
Current
I
CC
I
SB
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| KM68V1002CI | 128K x 8 Bit High-Speed CMOS Static RAM(3.3V Operating)(128K x 8位高速CMOS 靜態(tài) RAM) |
| KM68V257C | 32K x 8 Bit High-Speed CMOS Static RAM (3.3V Operating)(32K x 8位高速CMOS 靜態(tài) RAM) |
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|---|---|
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