參數(shù)資料
型號(hào): KM681001B-20
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 128K x 8 Bit High-Speed CMOS Static RAM
中文描述: 128K的× 8位高速CMOS靜態(tài)RAM
文件頁(yè)數(shù): 6/9頁(yè)
文件大?。?/td> 181K
代理商: KM681001B-20
KM681001B
CMOS SRAM
PRELIMINARY
Rev 2.0
- 6 -
February 1998
NOTES
(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. t
HZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V
OH
or
V
OL
levels.
4. At any given temperature and voltage condition, t
HZ
(Max.) is less than t
LZ
(Min.) both for a given device and from device to
device.
5. Transition is measured
±
200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS
1
=V
IL
and
CS
2
=V
IH.
7. Address valid prior to coincident with CS
1
transition low and CS
2
transition high.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1)
(OE= Clock)
Address
CS
1
CS
2
t
WP(2)
t
DW
t
DH
Valid Data
WE
Data in
Data out
t
WC
t
WR(5)
t
AW
t
CW(3)
High-Z(8)
High-Z
OE
t
OHZ(6)
t
AS(4)
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
CS
1
Address
OE
Data ou
t
CS
2
t
AA
t
OLZ
t
LZ(4,5)
t
OH
t
OHZ
t
RC
t
OE
t
CO
t
PU
t
PD
Valid Data
t
HZ(3,4,5)
50%
50%
V
CC
Current
I
CC
I
SB
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