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參數(shù)資料
| 型號(hào)： | KM616V1002CI |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 64K x 16 Bit High-Speed CMOS Static RAM(3.3V Operating)(64K x 16 位高速CMOS 靜態(tài) RAM(3.3V 工作)) |
| 中文描述： | 64K的× 16位高速CMOS靜態(tài)RAM（3.3V的工作）（64K的× 16位高速的CMOS靜態(tài)隨機(jī)存儲(chǔ)器（3.3V的工作）） |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 160K |
| 代理商： | KM616V1002CI |
KM616V1002C/CL, KM616V1002CI/CLI
CMOS SRAM
PRELIMINARY
PRELIMINARY
Revision 0.0
Aug. 1998
- 4 -
TEST CONDITIONS
NOTE: The above test conditions are also applied at industrial temperature range.
Parameter
Value
Input Pulse Levels
0V to 3.0V
Input Rise and Fall Times
3ns
Input and Output timing Reference Levels
1.5V
Output Loads
See below
AC CHARACTERISTICS
(T
A
=0 to 70
°
C, V
CC
=3.3
±
0.3V, unless otherwise noted.)
READ CYCLE
NOTE: The above parameters are also guaranteed at industrial temperature range.
Parameter
Symbol
KM616V1002C/CL-12
KM616V1002C/CL-15
KM616V1002C/CL-20
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time
t
RC
12
-
15
-
20
-
ns
Address Access Time
t
AA
-
12
-
15
-
20
ns
Chip Select to Output
t
CO
-
12
-
15
-
20
ns
Output Enable to Valid Output
t
OE
-
6
-
7
-
9
ns
UB, LB Access Time
t
BA
-
6
-
7
-
9
ns
Chip Enable to Low-Z Output
t
LZ
3
-
3
-
3
-
ns
Output Enable to Low-Z Output
t
OLZ
0
-
0
-
0
-
ns
UB, LB Enable to Low-Z Output
t
BLZ
0
-
0
-
0
-
ns
Chip Disable to High-Z Output
t
HZ
0
6
0
7
0
9
ns
Output Disable to High-Z Output
t
OHZ
0
6
0
7
0
9
ns
UB, LB Disable to High-Z Output
t
BHZ
0
6
0
7
0
9
ns
Output Hold from Address Change
t
OH
3
-
3
-
3
-
ns
Chip Selection to Power Up Time
t
PU
0
-
0
-
0
-
ns
Chip Selection to Power DownTime
t
PD
-
12
-
15
-
20
ns
Output Loads(B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
D
OUT
5pF*
319
353
+3.3V
* Including Scope and Jig Capacitance
Output Loads(A)
D
OUT
R
L
= 50
Z
O
= 50
V
L
= 1.5V
30pF*
* Capacitive Load consists of all components of the
test environment.
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