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參數(shù)資料
| 型號： | KM48S8030D |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 64Mbit SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM LVTTL |
| 中文描述： | 64Mbit SDRAM的200萬× 8位× 4銀行同步DRAM LVTTL |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 117K |
| 代理商： | KM48S8030D |
KM48S8030D
CMOS SDRAM
Rev. 0.0 May 1999
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T
A
= 0 to 70
°
C)
Parameter
Symbol
Test Condition
Version
Unit
Note
-A
-8
-H
-L
Operating current
(One bank active)
I
CC1
Burst length = 1
t
RC
≥
t
RC
(min)
I
O
= 0 mA
75
75
70
70
mA
1
Precharge standby current in
power-down mode
I
CC2
P
CKE
≤
V
IL
(max), t
CC
= 10ns
1
mA
I
CC2
PS
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
1
Precharge standby current in
non power-down mode
I
CC2
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
15
mA
I
CC2
NS
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
6
Active standby current in power-
down mode
I
CC3
P
CKE
≤
V
IL
(max), t
CC
= 10ns
3
mA
I
CC3
PS
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
3
Active standby current in
non power-down mode
(One bank active)
I
CC3
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
25
mA
I
CC3
NS
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
15
mA
Operating current
(Burst mode)
I
CC4
I
O
= 0 mA
Page burst
4Banks Activated
t
CCD
= 2CLKs
115
110
95
95
mA
1
Refresh current
I
CC5
t
RC
≥
t
RC
(min)
135
130
125
125
mA
2
Self refresh current
I
CC6
CKE
≤
0.2V
G
1
mA
3
F
400
uA
4
1. Measured with outputs open.
2. Refresh period is 64ms.
3. KM48S8030DT-G**
4. KM48S8030DT-F**
5. Unless otherwise noted, input swing IeveI is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ)
Notes :
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