參數(shù)資料
型號(hào): KM48C512D
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: High Speed 512K x 8Bit CMOS Dynamic RAM with with Fast Page Mode(高速512K x 8位 CMOS 動(dòng)態(tài)RAM(帶快速頁(yè)模式))
中文描述: 高速的CMOS為512k × 8位動(dòng)態(tài)隨機(jī)存儲(chǔ)器與快速頁(yè)面模式(高速為512k × 8位的CMOS動(dòng)態(tài)隨機(jī)存儲(chǔ)器(帶快速頁(yè)模式))
文件頁(yè)數(shù): 6/20頁(yè)
文件大?。?/td> 346K
代理商: KM48C512D
KM48C512D
CMOS DRAM
High Speed
AC CHARACTERISTICS
(Continued)
Parameter
Symbol
-4
Units
Notes
Min
Max
Data set-up time
t
DS
t
DH
t
REF
t
REF
t
CWD
t
RWD
t
AWD
t
CPWD
t
CSR
t
CHR
t
RPC
t
CPT
t
CPA
t
PC
t
PRWC
t
CP
t
RASP
t
RHCP
t
OEA
t
OED
t
OEZ
t
OEH
t
RASS
t
RPS
t
CHS
0
ns
9
Data hold time
10
ns
9
Refresh period (Normal)
16
ms
Refresh period (L-ver)
128
ms
CAS to W delay time
31
ns
7
RAS to W delay time
59
ns
7
Column address W delay time
39
ns
7
CAS precharge to W delay time
44
ns
7
CAS set-up time (CAS -before-RAS refresh)
10
ns
CAS hold time (CAS -before-RAS refresh)
10
ns
RAS to CAS precharge time
5
ns
CAS precharge time (C-B-R counter test cycle)
20
ns
Access time from CAS precharge
25
ns
3
Fast Page mode cycle time
28
ns
Fast Page read-modify-write cycle time
67
ns
CAS precharge time (Fast Page cycle)
6
ns
RAS pulse width (Fast Page cycle)
40
100K
ns
RAS hold time from CAS precharge
23
ns
OE access time
12
ns
OE to data delay
9
ns
Output buffer turn off delay time from OE
0
9
ns
6
OE command hold time
12
ns
RAS pulse width (C-B-R self refresh)
100
us
11,12,13
RAS precharge time (C-B-R self refresh)
74
ns
11,12,13
CAS hold time (C-B-R self refresh)
-50
ns
11,12,13
相關(guān)PDF資料
PDF描述
KM48C8004B 8M x 8bit CMOS Dynamic RAM with Extended Data Out
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KM44L32031BT-G(L)Z DDR SDRAM Specification Version 1.0
KM48L16031BT-G(L)Z DDR SDRAM Specification Version 1.0
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