參數(shù)資料
型號: KM44S16020B
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 8M x 4Bit x 2 Banks Synchronous DRAM(8M x 4位 x 2組同步動態(tài)RAM)
中文描述: 8米× 4位× 2銀行同步DRAM(8米× 4位× 2組同步動態(tài)RAM)的
文件頁數(shù): 2/43頁
文件大?。?/td> 597K
代理商: KM44S16020B
KM44S16020B
CMOS SDRAM
REV. 6 June '98
The KM44S16020B is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 2 x 8,388,608 words by 4 bits,
fabricated with SAMSUNG
s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem-
ory system applications.
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Dual banks operation
MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock
Burst read single-bit write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K Cycle)
GENERAL DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
8M x 4Bit x 2 Banks Synchronous DRAM
ORDERING INFORMATION
Part No.
Max Freq.
125MHz
100MHz
100MHz
100MHz
Interface Package
KM44S16020BT-G/F8
KM44S16020BT-G/FH
KM44S16020BT-G/FL
KM44S16020BT-G/F10
LVTTL
54
TSOP(II)
Samsung Electronics reserves the right to
change products or specification without
notice.
*
Bank Select
Data Input Register
8M x 4
8M x 4
S
O
I
Column Decoder
Latency & Burst Length
Programming Register
A
R
R
R
C
L
L
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
DQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
Timing Register
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