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參數(shù)資料
| 型號(hào)： | KM44C1004D |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1M x 4Bit CMOS Dynamic RAM with Extended Data Out(1M x 4位CMOS 動(dòng)態(tài)RAM(帶擴(kuò)展數(shù)據(jù)輸出)) |
| 中文描述： | 100萬x 4位的擴(kuò)展數(shù)據(jù)輸出的CMOS動(dòng)態(tài)RAM（3米× 4位的CMOS動(dòng)態(tài)隨機(jī)存儲(chǔ)器（帶擴(kuò)展數(shù)據(jù)輸出）） |
| 文件頁數(shù)： | 7/22頁 |
| 文件大?。?/td> | 399K |
| 代理商： | KM44C1004D |
KM44C1004D, KM44V1004D
CMOS DRAM
TEST MODE CYCLE
( Note 11 )
Note) *1 : t
CAC
=20ns@3.3V device / 18ns@5V device
Parameter
Symbol
-5
-6
-7
Units
Notes
Min
Max
Min
Max
Min
Max
Random read or write cycle time
t
RC
89
109
129
ns
Read-modify-write cycle time
t
RWC
121
145
170
ns
Access time from RAS
t
RAC
55
65
75
ns
3,4,10
Access time from CAS
t
CAC
*1
t
AA
20/18
*1
30
20
25
ns
3,4,5
Access time from column address
35
40
ns
3,10
RAS pulse width
t
RAS
55
10K
65
10K
75
10K
ns
CAS pulse width
t
CAS
13
10K
15
10K
20
10K
ns
RAS hold time
t
RSH
18
20
25
ns
CAS hold time
t
CSH
45
55
65
ns
Column Address to RAS lead time
t
RAL
30
35
40
ns
CAS to W delay time
t
CWD
35
39
49
ns
7
RAS to W delay time
t
RWD
72
84
94
ns
7
Column Address to W delay time
t
AWD
47
54
64
ns
7
Hyper Page mode cycle time
t
HPC
25
30
35
ns
15
Hyper Page mode read-modify-write cycle time
t
HPRWC
52
61
76
ns
RAS pulse width (Hyper Page cycle)
t
RASP
55
200K
65
200K
75
200K
ns
Access time from CAS precharge
t
CPA
33
40
45
ns
3
OE access time
t
OEA
t
OED
t
OEH
18
20
25
ns
OE to data delay
18
20
25
ns
OE command hold time
18
20
25
ns
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| KM44V1004D | 1M x 4Bit CMOS Dynamic RAM with Extended Data Out(1M x 4位CMOS 動(dòng)態(tài)RAM(帶擴(kuò)展數(shù)據(jù)輸出)) |
| KM44C1005D | 1M x 4Bit CMOS Quad CAS DRAM with Extended Data Out(1M x 4位CMOS四 CAS 動(dòng)態(tài)RAM(帶擴(kuò)展數(shù)據(jù)輸出)) |
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| KM44C256A-12 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256 x 4 Bit CMOS Dynamic RAM with Fast Page Mode |
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