參數(shù)資料
型號(hào)： KM432S2030CT-G8
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL
中文描述： 200萬(wàn)× 32內(nèi)存為512k × 32 × 4銀行同步DRAM LVTTL
文件頁(yè)數(shù)： 7/43頁(yè)
文件大?。?/td> 1161K
代理商： KM432S2030CT-G8
KM432S2030C
CMOS SDRAM
REV. 1.1 Mar. '99
- 7 -
AC OPERATING TEST CONDITIONS
(V
DD
= 3.3V
±
0.3V, T
A
= 0 to 70
°
C)
Parameter
Value
Unit
AC input levels (Vih/Vil)
2.4/0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall time
tr/tf = 1/1
ns
Output timing measurement reference level
1.4
V
Output load condition
See Fig. 2
3.3V
1200
870
Output
50pF
*1
V
OH
(DC) = 2.4V, I
OH
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
Vtt = 1.4V
50
Output
50pF
*1
Z0 = 50
(Fig. 2) AC output load circuit
(Fig. 1) DC output load circuit
1. The DC/AC Test Output Load of KM432S2030C-6/7 is 30pF.
2. The VDD condition of KM432S2030C-6 is 3.135V~3.6V.
Note :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer. Refer to the following clock unit based AC conversion table
Notes :
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Version
Unit
Note
-6
6
12
18
18
42
-7
7
14
18
18
49
-8
8
16
18
18
48
-10
10
20
20
20
50
CLK cycle time
Row active to row active delay
RAS to CAS delay
Row precharge time
t
CC(min)
t
RRD(min)
t
RCD(min)
t
RP(min)
t
RAS(min)
t
RAS(max)
t
RC
(
min
)
t
RDL(min)
t
CDL(min)
t
BDL(min)
t
CCD(min)
t
MRS(min)
ns
ns
ns
ns
ns
us
ns
CLK
CLK
CLK
CLK
CLK
1
1
1
1
Row active time
100
Row cycle time
Last data in to row precharge
Last data in to new col.address delay
Last data in to burst stop
Col. address to col. address delay
Mode Register Set cycle time
66
67
68
70
1
2
1
1
1
2
2
1
2,5
2
2
3
Number of valid output data
CAS Latency=3
CAS Latency=2
ea
4
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相關(guān)代理商/技術(shù)參數(shù)
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