參數(shù)資料
型號(hào): KM416C256D
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: CMF-55 24M 5% T-0 EK E3
中文描述: 256 × 16Bit的CMOS動(dòng)態(tài)RAM的快速頁面模式
文件頁數(shù): 8/8頁
文件大小: 83K
代理商: KM416C256D
KM416C256D, KM416V256D
CMOS DRAM
512cycle of burst refresh must be executed within 8ms before and after self refresh in order to meet refresh specification (L-
version).
tASC, tCAH are referenced to the earlier CAS rising edge.
tCP is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle.
tCWD is referenced to the later CAS falling edge at word red-modify-write cycle.
t
CWL
is specified from W falling edge to the earlier CAS rising edge.
t
CSR
is referenced to earlier CAS falling low before RAS transition low.
t
CHR
is referenced to the later CAS rising high after RAS transition low.
t
CSR
t
CHR
RAS
LCAS
UCAS
t
DS
t
DH
LCAS
DQ0 ~ DQ15
Din
20.
16.
15.
14.
11.
13.
12.
17.
t
DS
, t
DH
are specified for earlier CAS falling low.
UCAS
w
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