參數(shù)資料
型號： KM23C8100D
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 8M-Bit (1Mx8 /512Kx16) CMOS Mask ROM(8M位(1Mx8 /512Kx16) CMOS掩膜ROM)
中文描述： 800萬位（1Mx8 / 512Kx16）的CMOS掩模ROM（800萬位（1Mx8 / 512Kx16）的CMOS掩膜光盤）
文件頁數(shù)： 3/3頁
文件大?。?/td> 42K
代理商： KM23C8100D
KM23C8100D(G)
CMOS MASK ROM
TEST CONDITIONS
Item
Value
Input Pulse Levels
0.6V to 2.4V
Input Rise and Fall Times
10ns
Input and Output timing Levels
0.8V and 2.0V
Output Loads
1 TTL Gate and C
L
=100pF
AC CHARACTERISTICS
(T
A
=0
°
C to +70
°
C, V
CC
=5.0V
±
10%, unless otherwise noted.)
READ CYCLE
Item
Symbol
KM23C8100D(G)-10
KM23C8100D(G)-12
KM23C8100D(G)-15
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time
t
RC
100
120
150
ns
Chip Enable Access Time
t
ACE
100
120
150
ns
Address Access Time
t
AA
100
120
150
ns
Output Enable Access Time
t
OE
50
60
70
ns
Output or Chip Disable to
Output High-Z
t
DF
20
20
30
ns
Output Hold from Address Change
t
OH
0
0
0
ns
TIMING DIAGRAM
READ
ADD
A
0
~A
18
A
-1(*1)
CE
OE
D
OUT
D
0
~D
7
D
8
~D
15(*2)
ADD1
ADD2
VALID DATA
VALID DATA
t
OH
t
DF(*3)
t
RC
t
ACE
t
OE
t
AA
NOTES :
*1. Byte Mode only. A
-1
is Least Significant Bit Address.(BHE = V
IL
)
*2. Word Mode only.(BHE = V
IH
)
*3. t
DF
is defined as the time at which the outputs achieve the open circuit condition and is not referenced to V
OH
or V
OL
level.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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