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參數(shù)資料
| 型號： | KB2512 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| 中文描述： | 偏轉處理器多同步監(jiān)測儀 |
| 文件頁數(shù)： | 23/36頁 |
| 文件大?。?/td> | 365K |
| 代理商： | KB2512 |
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2512
22
OPERATING DESCRIPTION
GENERAL CONSIDERATIONS
Power Supply
The typical values of the power supply voltages Vcc and V
DD
are respectively 12V and 5V. Perfect operation is
obtained if Vcc and V
DD
are maintained in the limits: 10.8 to 13.2V and 4.5 to 5.5V.
In order to avoid erratic operation of the circuit during the transient phase of Vcc and V
DD
switching on, or switching
off, the value of Vcc and V
DD
are monitored and the outputs of the circuit are inhibited if Vcc is less than 7.5V
typically.
In the same manner, V
DD
is monitored and internal set-up is made until V
DD
reaches 4V (see I
2
C control table for
power on reset).
In order to have a very good power supply rejection, the circuit is internally powered by several internal voltage
references (the typical value is 8V). Two of these voltage references are externally accessible, one for the vertical
part and on one for the horizontal one. If needed, these voltage references can be used (until I
load
is less than
5mA). Furthermore it is necessary to filter the a.m. voltage references by the use of external capacitor connected to
ground, in order to minimize the noise and consequently the
“
jitter
”
on vertical and horizontal output signals.
I
2
C Control
KB251
2
belongs to the I
2
C controlled device family, instead of being controlled by DC voltage on dedicated control
pins, each adjustment can be realized through the I
2
C interface. The I
2
C bus is a serial bus with a clock and a data
input. The general function and the bus protocol are specified in the Phillips-bus data sheets.
The interface (data and clock) is TTL-level compatible. The internal threshold levels of the input comparator are
2.2V on rising edge and 0.8V on falling edge (when V
DD
is 5V). Spikes of up to 50ns are filtered by an integrator
and maximum clock speed is limited to 400kHz.
The data line (SDA) can be used in a bidirectional way that means in read-mode the IC clocks out a reply
information (1byte) to the micro-processor.
The bus protocol prescribes always a full-byte transmission. The first byte after the start condition is used to
transmit the IC-address (hexa 8C for write, 8D for read).
Write Mode
In write mode the second byte sent contains the sub address of the selected function to adjust (or controls to affect)
and the third byte the corresponding data byte. It is possible to send more than one data byte to the IC. If after the
third byte no stop or start condition is detected, the circuit increments automatically the momentary sub address in
the sub address counter by one (auto-increment mode). So it is possible to transmit immediately the next data
bytes without sending the IC address or sub address. It can be useful so as to reinitialize the whole controls very
quickly (flash manner). This procedure can be finished by a stop condition.
The circuit has 16 adjustment capabilities: 3 for horizontal part, 4 for vertical one, 2 for E/W correction, 2 for the
dynamic horizontal phase control, 1 for moire option, 3 for horizontal and vertical dynamic focus and 1 for B+
reference adjustment.
17 bits are also dedicated to several controls (on/off, horizontal forced frequency, sync priority, detection refresh
and XRAY reset).
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