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參數(shù)資料
| 型號： | KAD2708L-10Q68 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT 105MSPS SGL 68-QFN |
| 產(chǎn)品培訓(xùn)模塊： | High-Speed Analog-to-Digital Converters Solutions for Industrial Control Applications |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | FemtoCharge™ |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 105M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 196mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 68-QFN（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個差分，單極 |
12
FN6813.1
April 14, 2011
Functional Description
The KAD2708L is an 8-bit, 350MSPS A/D converter in a
pipelined architecture. The input voltage is captured by a
sample-and-hold circuit and converted to a unit of charge.
Proprietary charge-domain techniques are used to compare
the input to a series of reference charges. These
comparisons determine the digital code for each input value.
The converter pipeline requires 24 sample clocks to produce
a result. Digital error correction is also applied, resulting in a
total latency of 28 clock cycles. This is evident to the user as
a latency between the start of a conversion and the data
being available on the digital outputs.
At start-up, a self-calibration is performed to minimize gain
and offset errors. The reset pin (RST) is initially held low
internally at power-up and remains in that state until
calibration is complete. The clock frequency should remain
fixed during this time.
Calibration accuracy is maintained for the sample rate at
which it is performed and therefore should be repeated if the
clock frequency is changed by more than 10%. Recalibration
can be initiated via the RST pin, or power cycling, at any
time.
Reset
Recalibration of the ADC can be initiated at any time by
driving the RST pin low for a minimum of one clock cycle. An
open-drain driver is recommended.
The calibration sequence is initiated on the rising edge of
RST, as shown in Figure 21. The over-range output (ORP) is
set high once RST is pulled low, and it remains in that state
until calibration is complete. The ORP output returns to
normal operation at that time, so it is important that the
analog input be within the converter’s full-scale range in
order to observe the transition. If the input is in an
over-range state, the ORP pin stays high, and it is not
possible to detect the end of the calibration cycle.
While RST is low, the output clock (CLKOUTP/CLKOUTN)
stops toggling and is set low. Normal operation of the output
clock resumes at the next input clock edge (CLKP/CLKN)
after RST is deasserted. At 350MSPS, the nominal
calibration time is ~190ms.
Voltage Reference
The VREF pin is the full-scale reference, which sets the
full-scale input voltage for the chip and requires a bypass
capacitor of 0.1F or larger. An internally generated
reference voltage is provided from a bandgap voltage buffer.
This buffer can sink or source up to 50A externally.
An external voltage can be applied to this pin to provide a
more accurate reference than the internally generated
bandgap voltage or to match the full-scale reference among
a system of KAD2708L chips. One option in the latter
configuration is to use one KAD2708L's internally generated
reference as the external reference voltage for the other
chips in the system. Additionally, an externally provided
reference can be changed from the nominal value to adjust
the full-scale input voltage within a limited range.
To select whether the full-scale reference is internally
generated or externally provided, the digital input port,
VREFSEL, should be set appropriately: low for internal, or
high for external. This pin also has an internal 18k
Ω pull-up
resistor. To use the internally generated reference,
VREFSEL can be tied directly to AVSS, and to use an
external reference, VREFSEL can be left unconnected.
Analog Input
The fully differential ADC input (INP/INN) connects to the
sample-and-hold circuit. The ideal full-scale input voltage is
1.5VP-P, centered at the VCM voltage of 0.86V, as shown in
Figure 22.
Best performance is obtained when the analog inputs are
driven differentially. The common-mode output voltage,
VCM, should be used to properly bias each input, as shown
noise and distortion performance for wideband and/or high
intermediate frequency (IF) inputs. Two different transformer
FIGURE 21. CALIBRATION TIMING
CLKP
CLKN
CLKOUTP
RST
ORP
Calibration Begins
Calibration Complete
Calibration Time
FIGURE 22. ANALOG INPUT RANGE
1.0
1.8
0.6
0.2
1.4
INP
INN
VCM
0.86V
0.75V
-0.75V
V
t
KAD2708L
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