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參數(shù)資料
| 型號： | K7N161845M |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Kx36 & 1Mx18-Bit Pipelined NtRAMTM |
| 中文描述： | 512Kx36 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 468K |
| 代理商： | K7N161845M |
K7N163645M
K7N161845M
512Kx36 & 1Mx18 Pipelined N
t
RAM
TM
- 2 -
Rev 1.0
January 2000
512Kx36 & 1Mx18-Bit Pipelined N
t
RAM
TM
The K7N163645M and K7N161845M are 18,874,368-bits Syn-
chronous Static SRAMs.
The N
t
RAM
TM
, or No Turnaround Random Access Memory uti-
lizes all the bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-chip
write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily
stored by an edge triggered output register and then released
to the output buffers at the next rising edge of clock.
The K7N163645M and K7N161845M are implemented with
SAMSUNG
′
s high performance CMOS technology and is avail-
able in 100pin TQFP and 119BGA packages. Multiple power
and ground pins minimize ground bounce.
GENERAL DESCRIPTION
FEATURES
2.5V
±
5% Power Supply.
Byte Writable Function.
Enable clock and suspend operation.
Single READ/WRITE control pin.
Self-Timed Write Cycle.
Three Chip Enable for simple depth expansion with no data
contention .
A interleaved burst or a linear burst mode.
Asynchronous output enable control.
Power Down mode.
TTL-Level Three-State Outputs.
100-TQFP-1420A / 119BGA(7x17 Ball Grid Array Package).
FAST ACCESS TIMES
PARAMETER
Symbol -16 -15 -13 -10 Unit
Cycle Time
t
CYC
6.0 6.7 7.5
10
ns
Clock Access Time
t
CD
3.5 3.8 4.2 5.0
ns
Output Enable Access Time
t
OE
3.5 3.8 4.2 5.0
ns
N
t
RAM
TM
and No Turnaround Random Access Memory are trademarks of Samsung.
LOGIC BLOCK DIAGRAM
WE
BW
(x=a,b,c,d or a,b)
CLK
CKE
CS
1
CS
2
CS
2
ADV
OE
ZZ
DQa
~ DQd
or
DQa
0
~ DQb
8
DQPa ~ DQPd
ADDRESS
REGISTER
ADDRESS
REGISTER
C
L
A
′
0
~A
′
1
36 or 18
OUTPUT
REGISTER
BUFFER
DATA-IN
REGISTER
DATA-IN
REGISTER
K
K
K
BURST
ADDRESS
COUNTER
WRITE
ADDRESS
REGISTER
WRITE
CONTROL
LOGIC
C
R
K
A [0:18]or
A [0:19]
LBO
A
0
~A
1
A
2
~A
18
or
A
2
~A
19
512Kx36 , 1Mx18
MEMORY
ARRAY
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7N161845-QC13 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18-Bit Flow Through NtRAM |
| K7N161845-QC16 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18-Bit Flow Through NtRAM |
| K7N161845-QC20 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18-Bit Flow Through NtRAM |
| K7N161845-QC25 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18-Bit Flow Through NtRAM |
| K7N161845-QI13 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18-Bit Flow Through NtRAM |
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