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參數(shù)資料
| 型號(hào)： | K7J163682B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Kx36 & 1Mx18 DDR II SIO b2 SRAM |
| 中文描述： | 512Kx36 |
| 文件頁(yè)數(shù)： | 13/17頁(yè) |
| 文件大?。?/td> | 374K |
| 代理商： | K7J163682B |
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512Kx36 & 1Mx18 DDR II SIO b2 SRAM
- 13 -
Rev 3.1
July. 2004
K7J163682B
K7J161882B
TIMING WAVE FORMS OF READ,WRITE AND NOP
D3-1
1
2
3
4
5
6
7
8
NOP
READ
(burst of 2)
READ
(burst of 2)
WRITE
(burst of 2)
WRITE
(burst of 2)
READ
(burst of 2)
NOP
NOP
D3-2
D4-1
D4-2
Q1-1
Q1-2
Q2-1
Q2-2
t
DVKH
t
KHDX
t
DVKH
t
KHDX
t
CHQV
t
CHQV
t
CHQX1
t
CHQX
t
CHQX
t
CHQZ
Q5-1
Q5-2
t
CQHQV
t
KHKL
t
KLKH
t
KHKH
t
KHKH
t
CHCQV
t
CHCQX
t
CHCQX
t
KHCH
t
KHCH
t
KHKL
t
KLKH
t
KHKH
t
KHKH
t
IVKH
t
KHIX
A2
A1
A3
A4
A5
K
LD
R/W
K
A
D
Q
C
C
CQ
CQ
t
AVKH
t
KHAX
t
CHCQV
Qxx
Note
:
1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 i.e. the next internal burst address following A1+0.
2. Outputs are disabled one cycle after a NOP.
3. D3-1 refers to input to address A3+0, D3-2 refers to input to address A3+1, i.e the next internal burst address following A3+0.
4. If address A4=A5, data Q5-1=D4-1, data Q5-2=D4-2.
Write data is forwarded immediately as read results.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7J163682B-FC25000 | 制造商:Samsung Semiconductor 功能描述:SRAM Chip Sync Dual 1.8V 18M-Bit 512K x 36 0.45ns 165-Pin FBGA |
| K7J321882C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 DDR II SIO b2 SRAM |
| K7J321882C-FC27000 | 制造商:Samsung Semiconductor 功能描述:32M 32MSYNC DOUBLE DATA RATE, SEPARATE I/O X18 FBGA - Trays |
| K7J321882C-FC30T00 | 制造商:Samsung Semiconductor 功能描述:32MSYNC DDRII, SEPARATE I/O SRAMX18FBGA, T/R - Tape and Reel |
| K7J321882M | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 DDR II SIO b2 SRAM |
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