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參數(shù)資料
| 型號： | K7J161882B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Kx36 & 1Mx18 DDR II SIO b2 SRAM |
| 中文描述： | 512Kx36 |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 374K |
| 代理商： | K7J161882B |
512Kx36 & 1Mx18 DDR II SIO b2 SRAM
- 3 -
Rev 3.1
July. 2004
K7J163682B
K7J161882B
PIN CONFIGURATIONS
(TOP VIEW)
K7J163682B(512Kx36)
Notes :
1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 3A for 72Mb, 9A for 36Mb, 10A for 144Mb and 2A for 288Mb.
2. BW
0
controls write to D0:D8, BW
1
controls write to D9:D17, BW
2
controls write to D18:D26 and BW
3
controls write to D27:D35.
PIN NAME
1
2
3
4
5
6
K
7
8
9
10
11
CQ
A
CQ
V
SS/
SA*
NC
/
SA*
R/W
BW
2
BW
1
LD
NC/SA*
V
SS/
SA*
B
C
D
Q27
D27
D28
Q18
Q28
D20
D18
D19
Q19
SA
V
SS
V
SS
BW
3
SA
V
SS
K
SA
V
SS
BW
0
SA
V
SS
SA
V
SS
V
SS
D17
D16
Q16
Q17
Q7
D15
Q8
D8
D7
E
F
G
Q29
Q30
D30
D29
Q21
D22
Q20
D21
Q22
V
DDQ
V
DDQ
V
DDQ
V
SS
V
DD
V
DD
V
SS
V
SS
V
SS
V
SS
V
DD
V
DD
V
DDQ
V
DDQ
V
DDQ
Q15
D14
Q13
D6
Q14
D13
Q6
Q5
D5
H
J
K
Doff
D31
Q32
V
REF
Q31
D32
V
DDQ
D23
Q23
V
DDQ
V
DDQ
V
DDQ
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
V
DD
V
DD
V
DD
V
DDQ
V
DDQ
V
DDQ
V
DDQ
D12
Q12
V
REF
Q4
D3
ZQ
D4
Q3
L
M
N
P
Q33
D33
D34
Q35
Q24
Q34
D26
D35
D24
D25
Q25
Q26
V
DDQ
V
SS
V
SS
SA
V
SS
V
SS
SA
SA
V
SS
V
SS
SA
C
V
SS
V
SS
SA
SA
V
DDQ
V
SS
V
SS
SA
D11
D10
Q10
Q9
Q11
Q1
D9
D0
Q2
D2
D1
Q0
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
Notes:
1. C, C, K or K cannot be set to V
REF
voltage.
2. When ZQ pin is directly connected to V
DD
output impedance is set to minimum value
and it
cannot be connected to ground or left unconnected
.
3. Not connected to chip pad internally.
SYMBOL
K, K
C, C
PIN NUMBERS
6B, 6A
6P, 6R
DESCRIPTION
Input Clock
Input Clock for Output Data
NOTE
1
CQ, CQ
Doff
SA
11A, 1A
1H
Output Echo Clock
DLL Disable when low
Address Inputs
4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
D0-35
10P,11N,11M,10K,11J,11G,10E,11D,11C,10N,9M,9L
9J,10G,9F,10D,9C,9B,3B,3C,2D,3F,2G,3J,3L,3M,2N
1C,1D,2E,1G,1J,2K,1M,1N,2P
Data Inputs
Q0-35
11P,10M,11L,11K,10J,11F,11E,10C,11B,9P,9N,10L
9K,9G,10F,9E,9D,10B,2B,3D,3E,2F,3G,3K,2L,3N
3P,1B,2C,1E,1F,2J,1K,1L,2M,1P
Data Outputs
R/W
4A
Read, Write Control Pin, Read active
when high
LD
8A
Synchronous Load Pin, bus Cycle
sequence is to be defined when low
BW
0
, BW
1,
BW
2
, BW
3
7B,7A,5A,5B
Block Write Control Pin,active when low
V
REF
ZQ
V
DD
V
DDQ
2H,10H
11H
Input Reference Voltage
Output Driver Impedance Control Input
Power Supply ( 1.8 V )
Output Power Supply ( 1.5V or 1.8V )
2
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
V
SS
2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M,
8M,4N,8N
Ground
TMS
TDI
TCK
10R
11R
2R
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
TDO
NC
1R
JTAG Test Data Output
No Connect
3A, 9A
3
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