參數(shù)資料
型號: K6R4008V1B-C10
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: CMOS SRAM
中文描述: CMOS SRAM的
文件頁數(shù): 5/10頁
文件大小: 214K
代理商: K6R4008V1B-C10
K6R4008V1B-C/B-L, K6R4008V1B-I/B-P
CMOS SRAM
PRELIMINARY
Rev 2.2
May 1999
- 5 -
READ CYCLE*
* The above parameters are also guaranteed at industrial temperature range.
Parameter
Symbol
K6R4008V1B-10
K6R4008V1B-12
K6R4008V1B-15
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time
t
RC
10
-
12
-
15
-
ns
Address Access Time
t
AA
-
10
-
12
-
15
ns
Chip Select to Output
t
CO
-
10
-
12
-
15
ns
Output Enable to Valid Output
t
OE
-
5
-
6
-
7
ns
Chip Enable to Low-Z Output
t
LZ
3
-
3
-
3
-
ns
Output Enable to Low-Z Output
t
OLZ
0
-
0
-
0
-
ns
Chip Disable to High-Z Output
t
HZ
0
5
0
6
0
7
ns
Output Disable to High-Z Output
t
OHZ
0
5
0
6
0
7
ns
Output Hold from Address Change
t
OH
3
-
3
-
3
-
ns
Chip Selection to Power Up Time
t
PU
0
-
0
-
0
-
ns
Chip Selection to Power DownTime
t
PD
-
15
-
12
-
15
ns
TEST CONDITIONS*
* The above test conditions are also applied at industrial temperature range.
Parameter
Value
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3ns
Input and Output timing Reference Levels
1.5V
Output Loads
See below
AC CHARACTERISTICS
(T
A
=0 to 70
°
C, V
CC
=3.3
±
0.3V, unless otherwise noted.)
Output Loads(B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
D
OUT
5pF*
319
353
+3.3V
* Including Scope and Jig Capacitance
Output Loads(A)
D
OUT
R
L
= 50
Z
O
= 50
V
L
= 1.5V
30pF*
* Capacitive Load consists of all components of the
test environment.
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