參數(shù)資料
型號(hào): K6R3024V1D-HC10
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 128K x 24 Bit High-Speed CMOS Static RAM(3.3V Operating)
中文描述: 128K的× 24位高速CMOS靜態(tài)RAM(3.3V的工作)
文件頁(yè)數(shù): 5/9頁(yè)
文件大?。?/td> 172K
代理商: K6R3024V1D-HC10
K6R3024V1D
CMOS SRAM
Revision 1.0
December 2001
- 5 -
for AT&T
READ CYCLE*
Parameter
Symbol
K6R3024V1D-09
K6R3024V1D-10
K6R3024V1D-12
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time
t
RC
9
-
10
-
12
-
ns
Address Access Time
t
AA
-
9
-
10
-
12
ns
Chip Select to Output
t
CO
-
9
-
10
-
12
ns
Output Enable to Valid Output
t
OE
-
4
-
5
-
6
ns
Chip Enable to Low-Z Output
t
LZ
3
-
3
-
3
-
ns
Output Enable to Low-Z Output
t
OLZ
0
-
0
-
0
-
ns
Chip Disable to High-Z Output
t
HZ
0
4
0
5
0
6
ns
Output Disable to High-Z Output
t
OHZ
0
5
0
6
0
7
ns
Output Hold from Address Change
t
OH
3
-
3
-
3
-
ns
Chip Select to Power-Up Time
t
PU
0
-
0
-
0
-
ns
Chip Deselect to Power DownTime
t
PD
-
9
-
10
-
12
ns
WRITE CYCLE*
* This parameter is guaranteed by design but not tested.
These specifications are for the individual K6R3024V1D Static RAMs.
Parameter
Symbol
K6R3024V1D-09
K6R3024V1D-10
K6R3024V1D-12
Unit
Min
Max
Min
Max
Min
Max
Write Cycle Time
t
WC
9
-
10
-
12
-
ns
Chip Select to End of Write
t
CW
7
-
7
-
8
-
ns
Address Set-up Time
t
AS
0
-
0
-
0
-
ns
Address Valid to End of Write
t
AW
7
-
7
-
8
-
ns
Write Pulse Width(OE High)
t
WP
7
-
7
-
8
-
ns
Write Pulse Width(OE Low)
t
WP1
9
-
9
-
10
-
ns
Write Recovery Time
t
WR
0
-
0
-
0
-
ns
Write to Output High-Z
t
WHZ
0
5
0
5
0
5
ns
Data to Write Time Overlap
t
DW
5
-
5
-
7
-
ns
Data Hold from Write Time
t
DH
0
-
0
-
0
-
ns
End Write to Output Low-Z
t
OW
3
-
3
-
3
-
ns
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