參數(shù)資料
型號: K4R881869M-NbCcG6
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM
中文描述: 288Mbit RDRAM的為512k × 18位× 2 * 16屬銀行直接RDRAMTM
文件頁數(shù): 27/64頁
文件大?。?/td> 4084K
代理商: K4R881869M-NBCCG6
Page 25
Direct RDRAM
K4R881869M
Rev. 0.9 Jan. 2000
Preliminary
The second bubble type t
CBUB2
is inserted (as a NOCOP
command) by the controller between a WR and RD
command on the COL pins when there is a WR-WR-RD
sequence to the same device. This bubble enables write data
to be retired from the write buffer without being lost, and is
explained in detail in Figure 18. There would be no bubble if
address c0 and address d0 were directed to different devices.
This bubble appears on the DQA and DQB pins as t
DBUB2
between a write data dualoct D and read data dualoct Q. This
bubble also appears on the ROW pins as t
RBUB2
.
Control Register Transactions
The RDRAM has two CMOS input pins SCK and CMD and
two CMOS input/output pins SIO0 and SIO1. These provide
serial access to a set of control registers in the RDRAM.
These control registers provide configuration information to
the controller during the initialization process. They also
Figure 21: Interleaved Read Transaction with Two Dualoct Data Length
CTM/CFM
DQA8..0
DQB8..0
COL4
..COL0
ROW2
..ROW0
T
0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
T
15
T
16
T
20
T
24
T
28
T
17
T
21
T
25
T
29
T
18
T
22
T
26
T
30
T
19
T
23
T
27
T
31
T
32
T
36
T
40
T
44
T
33
T
37
T
41
T
45
T
34
T
38
T
42
T
46
T
35
T
39
T
43
T
47
ACT a0
PREX b3
RD c2
RD c1
RD b1
RD b2
PREX a3
ACT b0
ACT c0
ACT d0
ACT e0
RD a1
RD a2
PREX z3
RD d1
ACT f0
RDd2
PREX c3
RD e1
RD e2
PREX d3
RD z1
RD z2
PREX y3
Q (b2)
Q (b1)
Q (a2)
Q (a1)
Q (c1)
Q (c2)
Q (d1)
Q (z2)
Q (z1)
Q (x2)
Q (y1)
Q (y2)
t
RCD
t
CAC
Transaction e can use the
same bank as transaction a
t
RC
t
RR
f3 = {Da,Ba+2}
Transaction f: RD
f0 = {Da,Ba+2,Rf}
f1 = {Da,Ba+2,Cf1}
f2= {Da,Ba+2,Cf2}
e3 = {Da,Ba}
Transaction e: RD
e0 = {Da,Ba,Re}
e1 = {Da,Ba,Ce1}
e2= {Da,Ba,Ce2}
d3 = {Da,Ba+6}
Transaction d: RD
d0 = {Da,Ba+6,Rd}
d1 = {Da,Ba+6,Cd1}
d2= {Da,Ba+6,Cd2}
c3 = {Da,Ba+4}
Transaction c: RD
c0 = {Da,Ba+4,Rc}
c1 = {Da,Ba+4,Cc1}
c2= {Da,Ba+4,Cc2}
b3 = {Da,Ba+2}
Transaction b: RD
b0 = {Da,Ba+2,Rb}
b1 = {Da,Ba+2,Cb1}
b2= {Da,Ba+2,Cb2}
a3 = {Da,Ba}
Transaction a: RD
a0 = {Da,Ba,Ra}
a1 = {Da,Ba,Ca1}
a2= {Da,Ba,Ca2}
z3 = {Da,Ba+6}
Transaction z: RD
z0 = {Da,Ba+6,Rz}
z1 = {Da,Ba+6,Cz1}
z2= {Da,Ba+6,Cz2}
y3 = {Da,Ba+4}
Transaction y: RD
y0 = {Da,Ba+4,Ry}
y1 = {Da,Ba+4,Cy1}
y2= {Da,Ba+4,Cy2}
Figure 22: Interleaved RRWW Sequence with Two Dualoct Data Length
CTM/CFM
DQA8..0
DQB8..0
COL4
..COL0
ROW2
..ROW0
T
0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
T
15
T
16
T
20
T
24
T
28
T
17
T
21
T
25
T
29
T
18
T
22
T
26
T
30
T
19
T
23
T
27
T
31
T
32
T
36
T
40
T
44
T
33
T
37
T
41
T
45
T
34
T
38
T
42
T
46
T
35
T
39
T
43
T
47
ACT a0
MSK (b2)
WRA c2
MSK (b1)
WR c1
WR b1
MSK (y2)
WRA b2
PREX a3
D (b2)
D (b1)
ACT b0
ACT c0
ACT d0
ACT e0
RD a1
RD a2
PREX z3
Q (a2)
Q (a1)
MSK (c1)
D (c1)
NOCOP
MSK (c2)
RDd0
D (c2)
t
RBUB1
RDf1
Q (z2)
Q (z1)
D (y2)
RD z1
RD z2
t
CBUB1
t
DBUB1
t
DBUB1
t
DBUB2
t
CBUB2
t
RBUB2
t
CBUB2
NOCOP
Transaction e can use the
same bank as transaction a
f3 = {Da,Ba+2}
Transaction f: WR
f0 = {Da,Ba+2,Rf}
f1 = {Da,Ba+2,Cf1}
f2= {Da,Ba+2,Cf2}
e3 = {Da,Ba}
Transaction e: RD
e0 = {Da,Ba,Re}
e1 = {Da,Ba,Ce1}
e2= {Da,Ba,Ce2}
d3 = {Da,Ba+6}
Transaction d: RD
d0 = {Da,Ba+6,Rd}
d1 = {Da,Ba+6,Cd1}
d2= {Da,Ba+6,Cd2}
c3 = {Da,Ba+4}
Transaction c: WR
c0 = {Da,Ba+4,Rc}
c1 = {Da,Ba+4,Cc1}
c2= {Da,Ba+4,Cc2}
b3 = {Da,Ba+2}
Transaction b: WR
b0 = {Da,Ba+2,Rb}
b1 = {Da,Ba+2,Cb1}
b2= {Da,Ba+2,Cb2}
a3 = {Da,Ba}
Transaction a: RD
a0 = {Da,Ba,Ra}
a1 = {Da,Ba,Ca1}
a2= {Da,Ba,Ca2}
z3 = {Da,Ba+6}
Transaction z: RD
z0 = {Da,Ba+6,Rz}
z1 = {Da,Ba+6,Cz1}
z2= {Da,Ba+6,Cz2}
y3 = {Da,Ba+4}
Transaction y: WR
y0 = {Da,Ba+4,Ry}
y1 = {Da,Ba+4,Cy1}
y2= {Da,Ba+4,Cy2}
相關(guān)PDF資料
PDF描述
K4R881869M-NCK7 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM
K4R881869M-NCK8 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM
K4S280432A 128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL
K4S280432C 128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL
K4S280432F-UC 128Mb F-die SDRAM Specification 54 TSOP-II with Pb-Free (RoHS compliant)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K4R881869M-NCK7 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM
K4R881869M-NCK8 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM
K4R881869M-NCK8000 制造商:Samsung SDI 功能描述:
K4S160822D 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2Mx8 SDRAM 1M x 8bit x 2 Banks Synchronous DRAM LVTTL
K4S160822DT-G/F10 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2Mx8 SDRAM 1M x 8bit x 2 Banks Synchronous DRAM LVTTL