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參數(shù)資料
| 型號(hào)： | K4R881869D |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256/288Mbit RDRAM(D-die) |
| 中文描述： | 256/288Mbit的RDRAM（深模） |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 311K |
| 代理商： | K4R881869D |
Direct RDRAM
K4R571669D/K4R881869D
Page 13
Version 1.4 July 2002
t
CD
CTM/CFM stable after NAP/PDN entry
100
-
t
CYCLE
Figure 49
t
FRM
ROW packet to COL packet ATTN framing delay
7
-
t
CYCLE
Figure 48
t
NLIMIT
Maximum time in NAP mode
10.0
μ
s
Figure 47
t
REF
Refresh interval
32
ms
Figure 52
t
BURST
Interval after PDN or NAP (with self-refresh) exit in which all
banks of the RDRAM device must be refreshed at least once.
200
μ
s
Figure 53
t
CCTRL
Current control interval
34 t
CYCLE
100ms
ms/t
CYCLE
Figure 54
t
TEMP
Temperature control interval
100
ms
Figure 55
t
TCEN
TCE command to TCAL command
150
-
t
CYCLE
Figure 55
t
TCAL
TCAL command to quiet window
2
2
t
CYCLE
Figure 55
t
TCQUIET
Quiet window (no read data)
140
-
t
CYCLE
Figure 55
t
PAUSE
RDRAM device delay (no RSL operations allowed)
200.0
μ
s
page 38
a. MSE/MS are fields of the SKIP register. For this combination (skip override) the tDCW parameter range is effectively 0.0 to 0.0.
b.
t
S,MIN
and t
H,MIN
for other t
CYCLE
values can be interpolated between or extrapolated from the timings at the 2 specified t
CYCLE
values.
c. This parameter also applies to a-1066 part when operated with t
CYCLE
= 2.50ns
d. With V
IL,CMOS
=0.5V
CMOS
-0.4V and V
IH,CMOS
=0.5V
CMOS
+0.4V
e. Effective hold becomes t
H4
’=t
H4
+[PDNXA
64
t
SCYCLE
+t
PDNXB,MAX
]-[PDNX
256
t
SCYCLE
]
if [PDNX
256
t
SCYCLE
] < [PDNXA
64
t
SCYCLE
+t
PDNXB,MAX
]. See Figure 50.
Table 11: Timing Conditions
Symbol
Parameter
Min
Max
Unit
Figure(s)
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