參數(shù)資料
型號(hào)： K4C561638C-TCDA
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 256Mb Network-DRAM
中文描述： 256Mb的網(wǎng)絡(luò)內(nèi)存
文件頁(yè)數(shù)： 37/42頁(yè)
文件大?。?/td> 880K
代理商： K4C561638C-TCDA
K4C5608/1638C 256Mb Network-DRAM
REV. 0.7 Aug. 2003
- 37 -
Functional Description (Continued)
Address Inputs : A0 to A14
Address inputs are used to access the arbitrary address of the memory cell array within each bank. The Upper Addresses with Bank
address are latched at the RDA or WRA command and the Lower Addresses are latched at the LAL command. The A0 to A14 inputs
are also used for setting the data in the Regular or Extended Mode Register set cycle.
Data Input/Output : DQ0 to DQ7 or DQ15
The input data of DQ0 to DQ15 are taken in synchronizing with the both edges of DQS input signal.
The output data of DQ0 to DQ15 are outputted synchronizing with the both edges of DQS output signal.
Data Strobe : DQS or LDQS, UDQS
The DQS is bi-directional signal. Both edges of DQS are used as the reference of data input or output. The LDQS is allotted for Lower
Byte (DQ0 to DQ7) Data. The UDQS is allotted for Upper Byte(DQ8 to DQ15) Data. In write operation, the DQS used as an input signal
is utilized for a latch of write data. In read operation, the DQS that is an output signal provides the read data strobe.
Power Supply : Vdd, VddQ, Vss, VssQ
Vdd and Vss are supply pins for memory core and peripheral circuits.
VddQ and VssQ are power supply pins for the output buffer.
Reference Voltage : V
REF
V
REF
is reference voltage for all input signals.
Upper Address
A0 to A14
A0 to A14
Lower Address
A0 to A7
A0 to A6
K4C560838C-TC
K4C561638C-TC
相關(guān)PDF資料
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