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參數(shù)資料
| 型號(hào)： | K3N7C1000M-TC15 |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 MASK PROM, 150 ns, PDSO44 |
| 封裝： | 0.400 INCH, TSOP2-44 |
| 文件頁(yè)數(shù)： | 1/4頁(yè) |
| 文件大?。?/td> | 71K |
| 代理商： | K3N7C1000M-TC15 |
K3N7C1000M-TC
CMOS MASK ROM
Pin Name
Pin Function
A
0
- A
21
Address Inputs
Q
0
- Q
14
Data Outputs
Q
15
/A
-1
Output 15(Word mode)/
LSB Address(Byte mode)
BHE
Word/Byte selection
CE
Chip Enable
OE
Output Enable
V
CC
Power (+5V)
V
SS
Ground
64M-Bit (8Mx8 /4Mx16) CMOS MASK ROM
The K3N7C1000M-TC is a fully static mask programmable
ROM fabricated using silicon gate CMOS process technology,
and is organized either as 8,388,608 x 8 bit(byte mode) or as
4,194,304 x 16 bit(word mode) depending on BHE voltage
level.(See mode selection table)
This device operates with a 5V single power supply, and all
inputs and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
The K3N7C1000M-TC is packaged in a 44-TSOP2.
GENERAL DESCRIPTION
FEATURES
Switchable organization
8,388,608 x 8(byte mode)
4,194,304 x 16(word mode)
Fast access time : 120ns(Max.)
Supply voltage : single +5V
Current consumption
Operating : 70mA(Max.)
Standby : 50
μ
A(Max.)
Fully static operation
All inputs and outputs TTL compatible
Three state outputs
Package : K3N7C1000M-TC : 44-TSOP2-400
A
21
X
AND
DECODER
BUFFERS
A
0
Y
AND
DECODER
BUFFERS
MEMORY CELL
MATRIX
(4,194,304x16/
8,388,608x8)
SENSE AMP.
CONTROL
LOGIC
BUFFERS
A
-1
CE
OE
BHE
.
.
.
.
.
.
.
.
Q
0
/Q
8
Q
7
/Q
15
. . .
PIN CONFIGURATION
A
21
A
18
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE
V
SS
OE
Q
0
Q
8
Q
1
Q
9
Q
4
Q
12
Q
5
Q
13
Q
6
V
SS
Q
14
Q
7
Q
15
/A
-1
TSOP2
K3N7C1000M-TC
FUNCTIONAL BLOCK DIAGRAM
1
2
44
43
42
3
4
41
5
6
40
39
38
7
8
37
9
10
36
35
34
11
12
33
32
13
14
31
30
15
16
29
28
17
18
27
26
19
20
25
24
21
22
23
Q
2
Q
10
Q
3
Q
11
A
20
A
19
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
BHE
V
CC
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